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abaco systems PPC11A Hardware Reference Manual

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Contents
  1. document history
  2. about this manual
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Unpacking
  14. Figure 1-3 Product Label (Conduction-cooled Product)
  15. Configuration
  16. Inspection
  17. NVRAM Write Enable Link (P15 Pins 5 and 6)
  18. PMC1 & PMC2 5V VIO Selection Links (P15 Pins 13 to 16)
  19. Mezzanine Installation
  20. Installation and Power Up/Reset
  21. Connecting to PPC11A
  22. Functional Description
  23. Figure 4-2 Block Diagram (T2081)
  24. Figure 4-3 Block Diagram (T1042)
  25. Features
  26. Integrated Host Processor
  27. Memory Map
  28. Local Bus
  29. SDRAM
  30. Boot Flash
  31. SPI Serial Recovery Flash
  32. VME Interface
  33. VMEbus Master Access
  34. VMEbus Master Block Transfers (DMA)
  35. VMEbus Retries
  36. Ethernet
  37. Serial Communication Ports
  38. COM3 to COM6
  39. Host-to-BMM Serial Port
  40. SATA
  41. Table 4-16 GPIO Line Routing
  42. MIL-STD-1553
  43. Graphics
  44. Mezzanines
  45. XMCs
  46. Table 4-20 PMC/XMC Site 1 Signal Availability
  47. PMC/XMC Site 2 Configuration
  48. PCIe Infrastructure
  49. PCIe Switches
  50. Main Bus
  51. Sensor and Backplane Buses
  52. Processor Config EEPROM
  53. DIP Switches
  54. Real-Time Clock
  55. Timers
  56. AXIS Timer
  57. Resets and Interrupts
  58. External Interrupt
  59. FPGA
  60. JTAG
  61. LEDs
  62. DS10 and DS43 to DS45 (BIT)
  63. DS3 and DS4 (ETH0 Status)
  64. Air-cooled Front Panel (Build Levels 1 to 3)
  65. Control and Status Registers
  66. Board ID Register (Offset 0x600)
  67. Slave FPGA Revision Register (Offset 0x60B)
  68. Reset Cause Register 2 (Offset 0x61C)
  69. LED Control Register 1 (Offset 0x622)
  70. PCIe SATA SPI Control Register (Offset 0x626)
  71. NOR Flash Page Register (Offset 0x636)
  72. AXIS Clock Control Register (Offset 0x64F)
  73. Timer Data Byte Registers
  74. GPIO (7-0) Registers
  75. GPIO (7-0) Interrupt Both Edges Register (Offset 0x676)
  76. GPIO (7-0) Test Mode Register (Offset 0x67B)
  77. GPIO (15-8) Interrupt Polarity Register (Offset 0x681)
  78. GPIO (15-8) Test Mode Register (Offset 0x687)
  79. GPIO (23-16) Interrupt Enable Register (Offset 0x68B)
  80. GPIO (23-16) Availability Register (Offset 0x690)
  81. Availability Registers
  82. COM Port 4-Wire Configuration Register (Offset 0x6A2)
  83. USB2.0 Ports 7–0 Availability Register (Offset 0x6A5)
  84. VGA Availability Register (Offset 0x6AA)
  85. Front Panel Configuration Register (Offset 0x6AE)
  86. SSD Availability Register (Offset 0x6B1)
  87. COM Port Mode Register (Offset 0x6BC)
  88. SSD Erase Control Register (Offset 0x6BF)
  89. Test Register (Offset 0x6C7)
  90. XMC/PMC Site 1 Status Register (Offset 0x6C8)
  91. XMC/PMC Site 2 Status Register (Offset 0x6C9)
  92. SSD Status Register (Offset 0x6CB)
  93. Jumper Link Status Register (Offset 0x6CD)
  94. Boot Location Status Register (Offset 0x6CE)
  95. Alarm Status Register (Offset 0x6D1)
  96. Interrupt Status Register (Low) (Offset 0x6E0)
  97. Availability/Configuration Register (Offset 0x6E8)
  98. EEPROM DIP Switch 1 Configuration Register 0 (Offset 0x6EA)
  99. Configuration Unlock Password Register (Offset 0x6EC)
  100. Flash Password Registers (Offsets 0x6F0 to 0x6F7)
  101. Watchdog Prescaler (Low Byte) Register (Offset 0x701)
  102. Watchdog Kick Register (Offset 0x704)
  103. Watchdog Minimum Threshold Low Byte Register (Offset 0x70A)
  104. Scratchpad Memory Registers (Offset 0x720 to 0x72F)
  105. Connectors
  106. Figure 6-2 Rear Connector Position
  107. Backplane Connectors
  108. P1 Connector
  109. P2 Connector
  110. Backplane Signal Definitions
  111. Figure 6-3 RS422/485 Signal Waveforms
  112. PMC Connectors
  113. J13/J23 Connector
  114. J14/J24 Connector
  115. PMC Signal Descriptions
  116. XMC Connectors
  117. J16 Connector
  118. XMC Signal Descriptions
  119. Test and Programming Headers
  120. A • Specifications
  121. A.2 Electrical Specification
  122. A.3 Reliability (MTBF)
  123. A.5 Product Codes
  124. A.6 Software Support
  125. A.6.3 Background Condition Screening
  126. B • Statement of Volatility
  127. C • PPCx Compatibility
  128. C.1.2 P1 Connector
  129. C.1.3 P2 Connector
  130. C.1.4 P2 Connector Alternative
  131. C.2 PPC7A
  132. C.2.2 P1 Connector
  133. C.2.3 P2 Connector
  134. C.2.1 P2 Connector Alternative
  135. C.3 PPC7D
  136. C.3.2 P0 Connector Alternative
  137. C.3.3 P1 Connector
  138. C.3.4 P2 Connector
  139. C.3.1 P2 Connector Alternative
  140. C.4 PPC10A
  141. C.4.1 P0 Connector Alternative
  142. C.4.2 P1 Connector
  143. C.4.3 P2 Connector
  144. C.4.1 P2 Connector Alternative 1
  145. C.4.1 P2 Connector Alternative 2
  146. Glossary
  147. Index
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This manual is suitable for:
PPC11A