Toshiba TLCS-900/H1 Series Manual

Also see for TLCS-900/H1 Series: Manual Manual Data book Manual

TMP92CH212009-06-1992CH21-353Figure 3.14.10 Fastest Timing Diagram for External SRAM, 0 waits∗ When using internal SRAM, always select 32-bit bus width and 0 waits, 1 clocks access.Figure 3.14.11 Timing Diagram for Internal SRAMLCP0 (2CP)OUTLD7 to LD0 OUT OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 3 OUT + 4 OUT + 4Monochrome/4/16 grayscales/256 colors4-/8-bit bus16-bit bus width, monochrome/4 grayscales/256 colorsLCP0 (2CP)LCP0 (4CP)LD7 to LD0LCP0 (8CP)LD7 to LD016-bit bus, 16 grayscalesOUTLD7 to LD0 OUT OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 3 OUT + 4 OUT + 4OUT OUT + 1 OUT + 2 OUT + 3OUT32-bit bus width, monochrome/4 grayscales/256 colors8-bit busLCP0 (2CP)LCP0 (4CP)LD3 to LD016-bit bus, monochrome4/16 grayscales/256 colorsOUTLD3 to LD0 OUT OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 3 OUT + 4 OUT + 4OUT OUT + 1 OUT + 2 OUT + 332-bit bus, monochrome/4/16 grayscales/256 colors4-bit busA23 to A0RDD32 to D0 or D15 to D0Internal system clock(f SYS )NINN + 1 N + 2 N + 3 N + 4 N + 5IN + 1 IN + 2 IN + 3 IN + 4 IN + 5