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Sharp QA-1650 Service Manual
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C164a0 GluRiZ3 C18510 GlvR? BRIGHTO.tuFig.12 THRESHOLD LEVEL GENERATOR CIRCUIT5.PLL CIRCUITThe dot clock is needed to sample video signals from the computer so as to obtain appropriate dot data.The dot clock (f,,,) is generated by the PLL circuit in Fig.13. The horizontal sync (f,,) is compared with the feedbacksignal (f,) by the PHASE DETECTOR in IC1. When a phase or frequency error occurs between f,,and f.,|C1 PDBterminal (pin 122) is at a low or high level.When the phase and frequency of f,,corresponds with those of f., high impedance results. Output signal from thePDB terminal is converted into DC voltage which controls VCO(Voltage Controlled Oscillator), when passedthrough the LOOP FILTER.VCO is provided with two oscillators (SP1648).IC28 is the oscillator for high band (20.8 to 30.24 MHz), and IC29the oscillator for low band (14.4 to 20.8 MHz).For these oscillators, oscillation frequency is determined by varac-tor diode (D2 and 3) capacitance and coil (L3 and 4) inductance.Oscillation frequency is controlled by varyingvoltage applied on the varactor diode.Itis judged by IC2 pin 10 (VCOh) and pin 11 (VCOL) after amplified by transistor (Q6 and 7) which VCO (high orlow band) should be effective. The controlling voltage from the LOOP FILTER varies oscillation frequency ina di-rection to correct a phase error detected by the PHASE DETECTOR in IC1.VCOoutput(f,,.)issentto1C30 (74HCO00) andthento IC1pin123 (VCOIN),dividedto1/Nbythe 1/NVARIABLEDIVIDERandbecomesfeedbacksignalfF.ThefeedbacksignalisinputtedintothePHASEDETECTORin|C1andcomparedwith horizontalsync fH.Withthisloop repeated,VCOoutput (fx) inputted fromVCOINbecomesthedotsignalwhose phase agreeswith horizontalsyncf,,,andwhosefrequencyisNtimes as large asfH.DivisionratioNofthe 1/NVARIABLE DIVIDERiscontrolledbyIC1 register (F-latch)dependingon the valueseton|C2(M.P.U,).Theset value also can be controlled viakey input on the main bodyorREMOTE CONTROLUNIT.27 |
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