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S3C2500B
Samsung S3C2500B User Manual
Samsung S3C2500B User Manual
Table of content
Contents
important notice
Table Of Contents
chapter 3 instruction set
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
list of figures
list of tables
Overview
product overview
Features
block diagram
package diagram
Pin Assignment
signal description
Pad Type
Special Registers
memory formats
Instruction Length
Registers
The Relationship Between ARM and THUMB State Registers
Accessing Hi-Registers in THUMB State
The Condition Code Flags
Exceptions
Exception Entry/Exit Summary
Abort
Software Interrupt
Exception Priorities
Interrupt Latencies
Introduction for ARM940T
ARM940T Block Diagram
About The ARM940T Programmer's Model
Data Abort Model
ARM940T CP15 Registers
instruction set
Instruction Summary
The Condition Field
Branch and Exchange (BX)
Branch and Branch with Link (B, BL)
Assembler Syntax
Data Processing
CPSR Flags
Shifts
Immediate Operand Rotates
Instruction Cycle Times
PSR Transfer (MRS, MSR)
Reserved Bits
Multiply and Multiply-Accumulate (MUL, MLA)
Multiply Long and Multiply-Accumulate Long (MULL, MLAL)
Single Data Transfer (LDR, STR)
Offsets and Auto-Indexing
Use of R15
Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH)
Half-Word Load and Stores
Block Data Transfer (LDM, STM)
Addressing Modes
Use of R15 as the Base
Inclusion of the Base in the Register List
Single Data Swap (SWP)
Data Aborts
Software Interrupt (SWI)
Coprocessor Data Operations (CDP)
Coprocessor Data Transfers (LDC, STC)
Coprocessor Register Transfers (MRC, MCR)
Transfers to R15
Undefined Instruction
Instruction Set Examples
Pseudo-Random Binary Sequence Generator
Loading a Word From an Unknown Alignment
Thumb Instruction Set Format
Opcode Summary
Format 1: Move Shifted Register
Format 2: Add/Subtract
Format 3: Move/Compare/Add/Subtract Immediate
Format 4: ALU Operations
Format 5: Hi-Register Operations/Branch Exchange
Using R15 as an Operand
Format 6: PC-Relative Load
Format 7: Load/Store With Register Offset
Format 8: Load/Store Sign-Extended Byte/Half-Word
Format 9: Load/Store with Immediate Offset
Format 10: Load/Store Half-Word
Format 11: SP-Relative Load/Store
Format 12: Load Addres
Format 13: Add Offset to Stack Pointer
Format 14: Push/Pop Registers
Format 15: Multiple Load/Store
Format 16: Conditional Branch
Format 17: Software Interrupt
Format 18: Unconditional Branch
Format 19: Long Branch With Link
General Purpose Signed Divide
Division by a Constant
system configuration
address map
Remap of Memory Space
arbitration scheme
Problem Solvings with Programmable Round-Robin
Clock Configuration
External Bus Master
System Configuration Special Registers
System Configuration Register
Product Code and Revision Number Register
Clock Control Register
Peripheral Clock Disable Register
Clock Status Register
Core PLL Control Register
System Bus PLL Control Register
USB PLL Control Register
memory controller
memory map
Bus Interface Signals
Endian Modes
Ext I/O Bank Controller
External Device Connection
Ext. I/O Bank Controller Special Register
Timing Diagram
SDRAM Controller
SDRAM Size and Configuration
Address Mapping
SDRAM Commands
External Data Bus Width
Basic Operation
SDRAM Special Registers
SDRAM Controller Timing
functional description
General Characteristics
Data Validity
Data Trsansfer Operations
Control Status Register
Shift Buffer Register
Prescaler Counter Register
ethernet controller
MAC Function Blocks
Physical Layer Entity (PHY)
The MAC Receiver Block
Flow Control Block
Ethernet Controller Special Registers
BDMA Relative Special Register
MAC Relative Special Register
Ethernet Operations
The MII Station Manager
Full-Duplex Pause Operations
Error Signalling
Timing Parameters for MII Transactions
Function Descriptions
HDLC Frame Format
Protocol Features
FIFO Structure
Digital Phase-Locked Loop (DPLL)
HDLC Operational Description
HDLC Data Encoding/Decoding
HDLC Data Setup and Hold Timing with Clock
HDLC Transmitter Operation
HDLC Receiver Operation
Hardware Flow Control
Memory Data Structure
Data Buffer Descriptor
Buffer Descriptor
Receive Buffer Descriptor
HDLC Special Registers
HDLC Global Mode Register
HDLC Control Register
HDLC Status Register
HDLC Interrupt Enable Register
HDLC Tx Fifo
HDLC Rx Fifo
HDLC Brg Time Constant Registers
HDLC Preamble Constant Register
Dma Tx Buffer Descriptor Pointer Register
Dma Rx Buffer Descriptor Pointer Register
Receive Buffer Size Register
Transparent Control Register
Tx Buffer Descriptor Count Register
Tx Buffer Descriptor Maximum Count Register
IOM2 Bus
B Channels
Channel Operation
TSA (Time Slot Assigner)
HDLC External Pin Multiplexed Signals
IOM2 Special Registers
IOM2CON Register
IOM2 Status Register
IOM2 Interrupt Enable Register
IOM2 TIC Bus Address Register
IOM2 IC Channel Transmit Data Register
IOM2 C/I0 Channel Transmit Data Register
IOM2 C/I1 Channel Transmit Data Register
IOM2 Monitor Channel Transmit Data Register
TSA A Control Register
TSA B Control Register
TSA C Control Register
IOM2STRB (Strobe Register)
Packet Formats
Bit Stuffing and NRZI Coding
Control Transactions
USB Block Descriptions
USB Special Registers
USB Function Address Register
USB Power Management Register
USB Interrupt Register
USB Interrupt Enable Register
USB Frame Number Register
USB Disconnect Timer Register
USB Endpoint 0 Common Status Register
USB Endpoint 1 Common Status Register
USB Endpoint 2 Common Status Register
USB Endpoint 3 Common Status Register
USB Endpoint 4 Common Status Register
USB Write Count for Endpoint 0 Register
USB Write Count for Endpoint 1 Register
USB Write Count for Endpoint 2 Register
USB Write Count for Endpoint 3 Register
USB Write Count for Endpoint 4 Register
USB Endpoint 0/1/2/3/4 FIFO Register
DES/3DES Special Registers
DES/3DES Control Register
DES/3DES Status Register
DES/3DES Run Enable Register
DES/3DES Key 3 Left Side Register
DES/3DES Input/Output Data FIFO Register
DES/3DES Operation
Performance Calculation Guide
GDMA Special Registers
GDMA Programmable Priority Registers
GDMA Control Registers
GDMA Source/Destination Address Registers
GDMA Transfer Count Registers
GDMA Run Enable Registers
GDMA Interrupt Pending Register
GDMA Mode Operation
DES Mode
Data Transfer Modes
GDMA Transfer Timing Data
Single and One Data Burst Mode
Single and Four Data Burst Mode
Block and One Data Burst Mode
Block and Four Data Burst
Console UART Special Registers
Console UART Control Registers
Console UART Status Registers
Console UART Interrupt Enable Register
UART Transmit Data Register
UART Receive Data Register
UART Baud Rate Divisor Register
Console UART Baud Rate Examples
UART Control Character Register 1 and 2
High-Speed UART Special Registers
High-Speed UART Control Registers
High-Speed UART Status Registers
High-Speed UART Interrupt Enable Register
High-Speed UART Transmit Buffer Register
High-Speed UART Receive Buffer Register
High-Speed UART Baud Rate Divisor Register
High-Speed UART Baud Rate Examples
High-Speed UART Control Character 1 Register
High-Speed UART Control Character 2 Register
High-Speed UART Autoband Boundary Register
High-Speed UART Autobaud Table Regsiter
High-Speed UART Operation
Software Flow Control
I/O Port Mode Select Register
I/O Port Function Control Register
I/O Port Control Register for GDMA
I/O Port Control Register for External Interrupt
I/O Port External Interrupt Clear Register
I/O Port Data Register
interrupt controller
Interrupt Sources
Interrupt Controller Special Registers
Interrupt Mask Registers
Interrupt Priority Registers
Interrupt Offset Register
Interrupt by Priority Register
Interval Mode Operation
Timer Operation Guidelines
Timer Special Register
Timer Data Registers
Timer Count Registers
Timer Interrupt Clear Registers
Watchdog Timer Register
electrical data
DC Electrical Specifications
Max Power Consumption
AC Electrical Characteristics
mechanical data
21-S3C2500B-032003
USER'S MANUAL
S3C2500B
32-Bit RISC
Microprocessor
Revision 1
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This manual is suitable for:
S3C2500B
