Rabbit RabbitCore RCM2200 User Manual

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Rabbit RabbitCore RCM2200 User Manual Manual pdf 47 page image

User’s Manual 43C.2 Chip Select CircuitThe RCM2100 has provision for battery backup, which kicks in to keep VRAM fromdropping below 2 V.When the RCM2200 is not powered, the battery keeps the SRAM memory contents andthe real-time clock (RTC) going. The SRAM has a powerdown mode that greatly reducespower consumption. This powerdown mode is activated by raising the chip select (CS)signal line. Normally the SRAM requires Vcc to operate. However, only 2 V is requiredfor data retention in powerdown mode. Thus, when power is removed from the circuit, thebattery voltage needs to be provided to both the SRAM power pin and to the CS signalline. The CS control switch accomplishes this task for the CS signal line.Figure C-3 shows a schematic of the chip select control switch.Figure C-3. Chip Select Control SwitchIn a powered-up condition, the CS control switch must allow the processor’s chip selectsignal /CS1 to control the SRAM’s CS signal /CSRAM. So, with power applied, /CSRAMmust be the same signal as /CS1, and with power removed, /CSRAM must be held high(but only needs to be as high as the battery voltage). Q3 and Q4 are MOSFET transistorswith opposing polarity. They are both turned on when power is applied to the circuit. Theyallow the CS signal to pass from the processor to the SRAM so that the processor can peri-odically access the SRAM. When power is removed from the circuit, the transistors willturn off and isolate /CSRAM from the processor. The isolated /CSRAM line has a 100 kΩpullup resistor to VRAM (R28). This pullup resistor keeps /CSRAM at the VRAM voltagelevel (which under no power condition is the backup battery’s regulated voltage at a littlemore than 2 V).Transistors Q3 and Q4 are of opposite polarity so that a rail-to-rail voltages can be passed.When the /CS1 voltage is low, Q3 will conduct. When the /CS1 voltage is high, Q4 willconduct. It takes time for the transistors to turn on, creating a propagation delay. Thisdelay is typically very small, about 10 ns to 15 ns.&&: ),66 2+:D+:&F