661 2 3 41 2 3 4CDFABETS7, BCT-1710, BCT-1720, BCT-1730Note: 1 The following abbreviations are used: I - Input; O - Output; OD - Open drain output.2 3.3 V output levels.3 5 V tolerantPin Number Name I/O1 DescriptionSIGNAL INPUTS50, 51 IP, IN I Analog in Phase Component53, 54 QN, QP I Analog in Quadrature ComponentFRONT END CONTROLS1 CLK_IN/XTAL IN I Crystal Input or CLK_IN2 XTAL OUT O Crystal Output9 AGC OD3 Control Signal to the Tuner5 AUX_CLK O2 Programmable Output Port or Programmable Output Clock17-18 OP0, OP1 O2 Programmable Output Ports19 LOCK/OP2 O2 Carrier Found or Data Found or Output Port38 IP0 I Input PortSIGNAL OUPUTS26-28-29-31, 33 to 36 D[7:0] O2 Output Data; D7 is DATA_OUT in Serial Mode24 CLK_OUT O2 Output Byte Clock; or Bit Clock in Serial Mode22 STR_OUT O2 Output 1st byte Signal (synchro byte clock)21 D/P O2 Data/Parity Signal20 ERROR O2 Output Error Signal. Set in case of uncorrectible packet.I 2C INTERFACE14 SCL I3 Serial Clock (I2 C bus)12 SDA I/OD3 Serial Data (I2C bus)OTHERS59 SCLT OD3 Tuner Serial Clock (repeator) or Output Port60 SDAT I/OD3 Tuner Serial Data (repeator) or Input/Output Port37-43-44-45-46-61-62 TEST I Reserved for manufacturing tests; must be tied to V SS58 DIRCLK_DIS I Sets the DIRCLK function at power on3, 49, 52, 57 VSSA S Analog Ground4, 47, 55 VDDA S Analog 2.5 V Supply56 VTOP S ADC High Voltage Reference48 VBOT S ADC Low Voltage Reference6-8-11-23-27-32-39-64 V SS S Ground13-25 VDD_3.3 V S 3.3 V Supply7-10-30-41-63 VDD S 2.5 V Supply15 RESET I Reset, active at low level42 STDBY I Sets STDBY at power on16 F22/DiSEqC O2 DiSEqC modulation, 22 kHz Tone, ProgrammableOutput Port40 DAC O2 Programmable Digital to Analog Converter Output¶ Pin Functionwww . xiaoyu163. comQQ 376315150 992894298TEL 13942296513 992894298051513673QQTEL 13942296513 QQ 376315150 892498299TEL 13942296513 QQ 376315150 892498299http://www.xiaoyu163.comhttp://www.xiaoyu163.com