12.9. Main Block Diagram (5 of 6)! " # $ % & ' ()*+,-./012TX3PTX2P_BTX2PTX0P_BBUS_SWHDMI_HPD1TX2NTX0N_BNTSC/ATSC_SWTX1PTCLKP_BSD_BOOTHDMI_EEP_WPTX1NTCLKN_BSW_OFF_DETFPGA_MUTETX0NTX1N_BTX0PSP_RTX1P_BSP_LTX2N_BAV2_S_DETSDA0A_MUTEFPGA_IIC_RSTA_MON_DEFINV_ONTX3N_BINV_SOSTX3P_BPANEL_ONSCL0A_MUTEHP_IN_LHP_IN_RCEC_OFFHDMI_RSTFPGA_OKA_MON_DJTAG_TMSTCLKPTCLKNHDMI_MUTEJTAG_TCKTX3NHP_DETAV1_S_DETMAIN5VMAIN3.3VSTQ4002D2Q4120STB7VMAIN3.3VQ4121Q4003MAIN3.3VBUS_SW(L:DT EEPROM/H:NORMAL)62A_MUTE(L:MUTE)PROMA_MON_DEF(L:MUTE)PLLMAIN+1.5VHDMI_MUTE(H:MUTE)CEC_OFF(L:PLL UP)VCO IN89HDMI_HPD1(L:HPDT)76OUTCTL927412973IC400512683ASDIPFD OUT1SW_OFF_DET(L:DT RESET)SD_BOOT(H:SD BOOT)NTSC/ATSC_SW(L:ATSC/H:ANALOG)77INV_SOS(H:SOS)14DVDD75SCL0PHASEFREQUENCYDETECTORVCCSDA0SDA0VOLTAGECONTROLLEDOSCILLATORJTAG_TMS57CTL56 FPGA_MUTE(L:MUTE)53HDMI_EEP_WP(H:ENABLE)HDMI_RST(L:RESET)524FPGA_OK(H:FPGA SOS)5150CLK INFPGA_IIC_RST(L:RESET)495AV2_S_DET(L:DET)48DCLKAV1_S_DET(L:DET)ASD047NCONFIGNCE 212437VCCOUTNCS DCLK12812DATA33454125JTAG_TCK142343323141VCO OUT567HREF11HFEBMAIN+1.5VVCO5SSPLU40IC1804MAIN+2.5V39319336131635 HP_DET(L:DET)FPGA(HVPK/SS/LVDS)139IC400484MAIN+3.3V1313023FINA97MAIN+2.5V87AVDD14068841435FINBIC400314131VCCVCCIC180578VCC144108INV_ON(L:OFF/H:ON)NCSOPANEL_ON(L:OFF/H:ON)DATA0242322212728262529