JVC 330 Service Manual

Contents

Chapter 2—Functional DescriptionModel 330, 340SC and 370SC Service Manual 2-21shaped to be three (3) horizontal periods in length. This signal, /VSYNCSC (pulse-shaped vertical sync) is then sent to the SCB and the VPB.Adjustment CountersThe adjustment counters implement the following timing functions:Left side, right side, top side, and bottom side blanking.Vertical and horizontal timing for convergence correction and overlay.Pincushion and linearity correction timing.Vertical phase.DC restore timing.The four-(4) sides' blanking adjustments are accomplished by counting from theregenerated H and VSYNC signals respectively. Each adjustment is independent of theothers. Vertical blanking is accomplished by counting a specified number of horizontallines after the vertical sync signal out of the VSYNC Mux. The top blanking counts thecommanded number of lines then unblanks the picture. The bottom blanking counts thecommanded number of lines then blanks the image.Horizontal blanking is accomplished by counting a specified number of Hx224 clockpulses after the regenerated HSYNC pulse, /HSYNCR). The left side blanking counts thecommanded number of clock pulses then unblanks the image. The right blanking countsthe commanded number of clock pulses then blanks the image. The outputs from thesecounters are combined with a signal indicating PLL lock, into a composite blankingsignal VIDBLANK (high when the image is to be blanked) that is sent to the VPB. Theuser selects the actual position of the four sides' blanking by adjusting from the remotecontrol.The SCB calculates the number of clock pulses to count for each of the four sides basedon the input from the user, and sends those numbers to the appropriate counters via theIIC serial communication bus signals LBlank, RBlank, TBlank, and BBlank.Adjustment counters also generate the convergence correction and overlay addressgenerators’ timing signals. The correction bit-map address counter's MAPST (timingpulse to tell the correction and overlay address generators to start a new frame) timingpulse is generated by counting the commanded number of /HSYNCR pulses since thevertical deflection flyback start pulse. The /CORSTRT (signal that indicates to the SCBwhen to start the correction and overlay address generators counting) timing signal is apulse signal sent to the SCB. Its timing is determined by counting the commandednumber of Hx224 pulses after the /HSYNCR signal.The position of the overlays (including menus and test patterns) and correction maps iscontrolled automatically in the vertical direction. In the horizontal direction, the usercontrols the position via the MENU POSITION selection under the TIMING SETUPMENU. This circuit also determines the phase between the regenerated HSYNC and theHV Flyback from Deflection. This value is read by the SCB over the IIC bus.The pincushion and linearity correction timing signal is a pulse signal called /PCST thatis sent to the Vertical Deflection Board. The signal is generated using the same timing