AT24C01A/02/04/08A/16ANote: 1. This parameter is characterized and is not 100% tested (TA = 25°C).2. This parameter is characterized.Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see toFigure 4 on page 7). Data changes during SCL high periods will indicate a start or stopcondition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start conditionwhich must precede any other command (see to Figure 5 on page 7).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby powermode (see Figure 5 on page 7).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from theEEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has receivedeach word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby modewhich is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and thecompletion of any internal operations.Table 5. AC CharacteristicsApplicable over recommended operating range from T A = −40°C to +125°C, V CC = +2.7V to +5.5V, CL = 1 TTL Gate and100 pF (unless otherwise noted)Symbol ParameterAT24C01A/02/04/08A/16AUnitsMin Maxf SCL Clock Frequency, SCL 400 kHzt LOW Clock Pulse Width Low 1.2 μst HIGH Clock Pulse Width High 0.6 μst I Noise Suppression Time (1) 50 nst AA Clock Low to Data Out Valid 0.1 0.9 μst BUFTime the bus must be free beforea new transmission can start (2) 1.2 μst HD.STA Start Hold Time 0.6 μst SU.STA Start Set-up Time 0.6 μst HD.DAT Data In Hold Time 0 μst SU.DAT Data In Set-up Time 100 nst R Inputs Rise Time(2) 300 nst F Inputs Fall Time(2) 300 nst SU.STO Stop Set-up Time 0.6 μst DH Data Out Hold Time 50 nst WR Write Cycle Time 5 msEndurance(2) 5.0V, 25°C, Page Mode 1M Write Cyclesharman/kardonService manual DVD37EUPage 87 of 117