I nte r r upt Sys tern1 CSSet during execution of DISP instructionReset during execution of IXIT or PSEBinstructions.Set by microcode if Dispatcherwas interrupted.~01 &1 ~O (G)D DB-BankD DBFirst INT DEVNO~~ .~DCBAX~PI STATUSa 81 ~o../" DB-BankDBSecond INT OEVNOFigure 8-4. Second Level Interrupt or Dispatcher Interruptedg. The CPU obtains the device number from the Interrupt AddressRegister in the lOP and calculates the address of the DRTentry. DB is set to the DBI value in the third word of theDRT entry (7).h. The Status Register (8) is set to privileged mode, externalinterrupts enabled (%140000).i. The DB-Bank Register (9) is set to O.j. The S Register is set to point at location Q+3 (10) and thedevice number of the interrupting device is stored into thislocation. At this point, the ICS is fully delimited by reg-ister values and is ready for handling interrupt data.k. The external program label for the interrupt receiver code isfetched from the second word of the DRT entry. The CST entryis obtained from the segment number in the external programlabel. Then, the PB-Bank Register (11) is set based on theCST entry.1. The PB Register (12) is set based on the CST entry.m. The PL Register (13) is set based on the CST entry.8-11