FUJITSU SEMICONDUCTORCONTROLLER MANUALF 2MC-16LX16-BIT MICROCONTROLLERMB90580 SERIESHARDWARE MANUAL

Fujitsu F2MC-16LX MB90580 Series Hardware Manual

user guide

revision history

F2MC-16LX Series

REVISION HISTORY

WARRANTY AND DISCLAIMER

INTRODUCTION

OVERVIEW

Features Compared to MB2141A/B, MB2147-01

HARDWARE INSTALLATION

System Set-up

System Configuration

Supply of Clocks to the evaluation Chip

Example Configuration

SOFTWARE INSTALLATION

SET-UP DEBUG CONFIGURATION

APPENDIX

CHAPTER 1 OVERVIEW

Feature of MB90330 Series

Block Diagram

Package Dimension

Pin Assignment

Pin Function

I/O Circuit Types

Handling of Device

CHAPTER 2 CPU

Outline Specification of CPU

Memory Space

Register of CPU

Accumulator (A)

User Stack Pointer (USP) and System Stack Pointer (SSP)

Processor Status (PS)

Program Counter (PC)

Program Bank Register (PCB)

Direct Page Register (DPR)

General-purpose Registers (Register Bank)

Prefix Code

CHAPTER 3 INTERRUPT

Outline of Interrupt

Interrupt Cause and Interrupt Vector

Interrupt Control Register and Peripheral Function

Interrupt Control Registers (ICR00 to ICR15)

Interrupt Control Register Functions

Hardware Interrupt

Operation of Hardware Interrupt

Operation Flow of Hardware Interrupt

Procedure for Using a Hardware Interrupt

Multiple Interrupts

Hardware Interrupt Processing Time

Software Interrupt

Operation of Extended Intelligent I/O Service (EI 2 OS)

Exception Processing Interrupt

Interruption by µDMAC

µDMAC Function

Register of µDMAC

DMA Descriptor Channel Specification Register (DCSR)

DMA Status Register (DSRH/DSRL)

DMA Stop Status Register (DSSR)

DMA Permission Register (DERH/DERL)

DMA Descriptor Window Register (DDWR)

DMA Data Counter (DDCTH/DDCTL)

DMA I/O Register Address Pointer (DIOAH/DIOAL)

DMA Control Register (DMACS)

DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL)

Explanation of Operation of µDMAC

Exceptions

Stack Operation of Interrupt Processing

Program Example of Interrupt Processing

Delayed Interrupt Generation Module

Operation of Delayed Interrupt Generation Module

CHAPTER 4 RESET

Outline of Reset

Reset Factors and Oscillation Stabilization Wait Times

External Reset Pin

Reset Operation

Reset Factor Bit

State of Each Pin at Reset

CHAPTER 5 CLOCK

Outline of Clock

Block Diagram of Clock Generation Section

Clock Select Register (CKSCR)

Clock Mode

Oscillation Stabilization Wait Time

Connection of Oscillator and External Clock

CHAPTER 6 LOW-POWER CONSUMPTION MODE

Outline of Low-Power Consumption Mode

Block Diagram of Low-power Consumption Control Circuit

Low-power Consumption Mode Control Register (LPMCR)

CPU Intermittent Operation Mode

Standby Mode

Sleep Mode

Timebase Timer Mode

Watch Mode

Stop Mode

State Transition Diagram

State of the Pin during Standby Mode, Hold, and Reset

Precautions when Using Low-power Consumption Mode

CHAPTER 7 MODE SETTING

Mode Setting

Mode Pins (MD2 to MD0)

Mode Data

External Memory Access

Automatic Ready Function Selection Register (ARSR)

External Address Output Control Register (HACR)

Bus Control Signal Selection Register (EPCR)

Operation in Each Mode of Mode Setting

External Memory Access Control Signal

Ready Function

Holding Function

Features

Available Models

External Dimensions of the Package

Description of the Pin Functions

Cautions on Handling Devices

Addressing

Allocating Multiple-byte Data in a Memory Space

Dedicated Registers

Bank registers (PCB, DTB, USB, SSB, ADB)

General-purpose Registers

Prefix Codes

Interrupt Suppression Instructions and Prefix Codes

Notes on Using the "DIV A, Ri" and "DIVW A, RWi" Instructions

CHAPTER 3 INTERRUPTS

Overview of Interrupts

Interrupt Causes

Interrupt Vectors

Hardware Interrupts

Operation of Hardware Interrupts

Operating Flow for Hardware Interrupts

Example of Procedure for Using Hardware Interrupts

Software Interrupts

Interrupt Control Register (ICR)

Expanded Intelligent I/O Service (EI 2 OS)

Exceptions because of Executing Undefined Instructions

CHAPTER 4 GENERATING AND RESETTING CLOCKS

Clock Generator

Clock Supply Map

Reset Causes

Operation after a Reset is Released

Registers not Initialized by Reset Input

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT

Overview of the Low-power Consumption Control Circuit

Clock Selection Register (CKSCR)

Operation of the Low-power Consumption Control Circuit

Hardware Standby Mode

Pin status in the Sleep, Stop, Hold, Reset, and Hardware Standby Modes

Intermittent CPU Operation Function

Setting the Oscillation Stabilization Time

Machine Clock

CHAPTER 6 MEMORY ACCESS MODES

Memory Access Mode Overview

Mode Pins

Memory Space for Each Bus Mode

External Memory Access (External Bus Pin Control Circuit)

Registers for External Memory Access (External Bus Pin Control Circuit)

Bus Control Signal Selection Register (ECSR)

Operation of the External Memory Access Control Signals

Hold Function

CHAPTER 7 I/O PORTS

I/O Port Overview

I/O Port Block Diagram

I/O Port Registers

Port Data Registers (PDRx)

Port Data Direction Registers (DDRx)

Output Pin Register (ODR4)

Input Resistor Registers (RDR0 and RDR1)

Analog Input Enable Register (ADER)

CHAPTER 8 TIME-BASED TIMER

Overview of the Time-Based Timer

Time-Based Timer Control Register (TBTC)

Time-Based Timer Operations

CHAPTER 9 WATCHDOG TIMER

Overview of the Watchdog Timer

Watchdog Timer Control Register (WDTC)

Watchdog Timer Operations

CHAPTER 10 16-BIT I/O TIMER

Overview of the 16-Bit I/O Timer

Bit I/O Timer Block Diagram

Bit I/O Timer Registers

bit Free-run Timer

Output Compare

Input Capture

Bit Free-Run Timer Operations

Bit Output Compare Operations

CHAPTER 1 OVERVIEW OF MB90470

Overview

Block Diagram of MB90470

Package Dimensions

Pin Functions

I/O Circuit Type

Handling the Device

Overview of CPU Specifications

CPU Registers

Program Count Bank Register (PCB)

General-Purpose Register (Register Bank)

Interrupt Factor and Interrupt Vector

Interrupt Control Register (ICR00 to ICR15)

Hardware Interrupt Operation

Flow of Hardware Interrupt Operation

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