Fujitsu CS90A User Manual

130nm node CMOS Process (CS90A)Technology RoadmapFeaturesTechnology Code CS90ATransistor UHS HS ST LLPhysical Gate Length (nm) 110 110 110 110Gate Oxide Thickness (nm) 2.9 2.9 2.9 2.9Supply Voltage (V) 1.2 1.2 1.2 1.2NMOS Ids (μA/μm) 780 678 570 390PMOS Ids (μA/μm) -321 -276 -218 -150NMOS Ioff (nA/μm) 36 4 0.18 0.005PMOS Ioff (nA/μm) -18 -3.1 -0.22 -0.015Gate Leak Current (nA/μm) 0.01 0.01 0.01 0.01Basic Gate Delay (ps) 14 17 28 45Number of Available Poly Layer 1Number of Available Metal Layer 8Cu+1AlVia Filling Cu Dual DamasceneILD Structure Hybrid Low-kSRAM Cell Size (μm2) 1.98Dual Gate Oxide Options AvailableMixed Signal Options AvailableRF Elements MIM cap., Poly Resistor, InductorFuse RAM Redundancy180-nmCu 130-nmCu+Low+k 90-nmCu+VLK 65-nm 45-nm 32-nmCS80/80A10005002001005020101998 2000G: Generic, LL: Low Leakage2002 2004 2006 2008 2010 2012CS90ACS100A_LL For ASIC & COTYear (Production Start)Physical Gate Length (nm)For COTCS200A_LLCS200A_GCS200CS100CS90CS100A_GMie plant

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