Epson Arm S1C31 Series Technical Manual

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERSS1C31D41 TECHNICAL MANUAL Seiko Epson Corporation AP-A-23(Rev. 1.1)Address Register name Bit Bit name Initial Reset R/W Remarks0x002003a8T16_1TC(T16 Ch.1 CounterData Register)15–0 TC[15:0] 0xffff H0 R –0x002003aaT16_1INTF(T16 Ch.1 InterruptFlag Register)15–8 – 0x00 – R –7–1 – 0x00 – R0 UFIF 0 H0 R/W Cleared by writing 1.0x002003acT16_1INTE(T16 Ch.1 InterruptEnable Register)15–8 – 0x00 – R –7–1 – 0x00 – R0 UFIE 0 H0 R/W0x0020 03b0–0x0020 03be Synchronous Serial Interface (SPIA) Ch.0Address Register name Bit Bit name Initial Reset R/W Remarks0x002003b0SPIA_0MOD(SPIA Ch.0 ModeRegister)15–12 – 0x0 – R –11–8 CHLN[3:0] 0x7 H0 R/W7–6 – 0x0 – R5 PUEN 0 H0 R/W4 NOCLKDIV 0 H0 R/W3 LSBFST 0 H0 R/W2 CPHA 0 H0 R/W1 CPOL 0 H0 R/W0 MST 0 H0 R/W0x002003b2SPIA_0CTL(SPIA Ch.0 ControlRegister)15–8 – 0x00 – R –7–2 – 0x00 – R1 SFTRST 0 H0 R/W0 MODEN 0 H0 R/W0x002003b4SPIA_0TXD(SPIA Ch.0 TransmitData Register)15–0 TXD[15:0] 0x0000 H0 R/W –0x002003b6SPIA_0RXD(SPIA Ch.0 ReceiveData Register)15–0 RXD[15:0] 0x0000 H0 R –0x002003b8SPIA_0INTF(SPIA Ch.0 InterruptFlag Register)15–8 – 0x00 – R –7 BSY 0 H0 R6–4 – 0x0 – R3 OEIF 0 H0/S0 R/W Cleared by writing 1.2 TENDIF 0 H0/S0 R/W1 RBFIF 0 H0/S0 R Cleared by reading theSPIA_0RXD register.0 TBEIF 1 H0/S0 R Cleared by writing to theSPIA_0TXD register.0x002003baSPIA_0INTE(SPIA Ch.0 InterruptEnable Register)15–8 – 0x00 – R –7–4 – 0x0 – R3 OEIE 0 H0 R/W2 TENDIE 0 H0 R/W1 RBFIE 0 H0 R/W0 TBEIE 0 H0 R/W0x002003bcSPIA_0TBEDMAEN(SPIA Ch.0 TransmitBuffer Empty DMARequest EnableRegister)15–8 – 0x00 – R –7–4 – 0x0 – R3–0 TBEDMAEN[3:0] 0x0 H0 R/W0x002003beSPIA_0RBFDMAEN(SPIA Ch.0 ReceiveBuffer Full DMARequest EnableRegister)15–8 – 0x00 – R –7–4 – 0x0 – R3–0 RBFDMAEN[3:0] 0x0 H0 R/W