ADLINK Technology cPCI-7200 User Manual

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ADLINK Technology cPCI-7200 User Manual Manual pdf 34 page image

24 • Operation Theorem4.2 Timer Pacer ModeThe digital I/O access control is clocked by timer pacer, which is generated byan interval programming timer/counter chip 8254. There are three timers onthe 8254. The timer 0 is used to generate timer pacer for digital input, and timer1 is used for digital output. The configuration is illustrated as below.Timer 0Timer 1Timer 2CLK0GATE0 OUT0CLK1GATE1CLK2GATE2OUT1OUT28254 Timer/CounterDigital Input Timer PacerDigital Output Timer Pacer4MHz Clock“H”“H”“H”The operation sequences are:1. Define the frequency (timer pacer rate)2. The digital input data are saved in FIFO after a timer pacer pulse isgenerated. The sampling is controlled by timer pacer.3. The data saved in FIFO will be transferred to main memory of your computersystem directly and automatically. This is controlled by bus mastering DMAcontrol, this function is supported by PCI controller chip.The operation flow is show as following:Timer 0CLK0GATE0 OUT08254 Timer/CounterTo Digital Input TriggerLatch Digital InputDigital Input FIFOBus masteringDMA data TransferPC's Main Memory123