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Toshiba TX3904 manuals

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TX3904

Brand: Toshiba | Category: Computer Hardware
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. INTRODUCTION
  8. Notation used in this manual
  9. Kind of accessing by the TX3904
  10. Precautions in the TMPR3904F specification
  11. FEATURES
  12. CONFIGURATION
  13. Positions of Pins
  14. Functions of Pins
  15. ADDRESS MAPS
  16. Register Map
  17. Chip Configuration Register
  18. PIO2 and PIO1
  19. Error processing
  20. Connection of external bus master
  21. INT[7:0] active status set-up
  22. CLOCK
  23. Doze mode
  24. Status Shifting
  25. Operations of each block in the each modes
  26. BUS OPERATIONS
  27. Single read operation
  28. Burst read operation
  29. Single write operation
  30. Bus Error
  31. bit Bus Mode
  32. Half Speed Bus Mode
  33. Bus Arbitration
  34. Release of bus ownership
  35. Kinds of bus ownership
  36. Snoop function
  37. Interrupts
  39. Block Diagrams
  40. Registers
  41. Explanations of Registers
  42. Base address mask register 0 (DBMR0)
  43. Wait register 0 (DWR0)
  44. Channel control register 1 (DCCR1)
  45. Base address mask register 1 (DBMR1)
  46. Wait register 1 (DWR1)
  47. Refresh control register (DREFC)
  48. Operations
  49. Address multiplex
  50. Operation modes
  51. bit static bus sizing
  52. Page mode support and page hit detection
  53. Arbiter
  54. Timing Diagrams
  55. bit word single read operation with 16-bit bus
  56. bit bus fast page mode read (Burst mode)
  57. bit bus fast page mode read (Burst read) page hit miss
  58. bit bus hyper page mode read (Burst read)
  59. bit bus single write (Early write)
  60. bit bus fast page mode write (Early write)
  61. CBR refresh
  62. External Circuit Connections
  66. Channel control register 0
  67. Channel control register 1
  68. Base address mask register 0
  69. Base address mask register 1
  74. bit bus single read (32-bit word) operation (ROM/SRAM)
  75. bit bus single read (half word) operation (ROM/SRAM)
  76. bit bus single write (word) operation (SRAM/Flush)
  77. bit bus normal mode burst read operation (ROM/SRAM)
  78. bit bus page mode burst read operation (Page mode MROM)
  79. bit bus word normal mode burst read operation (ROM/SRAM)
  80. bit bus page mode burst read (word) operation (Page mode MROM)
  81. bit bus normal mode burst write (SRAM)
  82. bit bus normal mode burst write (word) (SRAM; WE control write)
  83. bit bus normal mode burst write (half word) (SRAM; WE control)
  84. Examples of MROM/EPROM Usage
  85. Examples of SRAM Usage
  86. DMA CONTROLLER (DMAC)
  88. DMAC internal blocks
  90. DMA control register (DCR)
  91. Channel control register (CCRn)
  92. Channel status register (CSRn)
  93. Source address register (SARn)
  94. Destination address register (DARn)
  95. Byte count register (BCR0n)
  96. Next byte count register (NCR0/1)
  97. Data holding register (DHR)
  98. Functions
  99. Transfer requests
  100. Address modes
  101. Burst transfer
  102. Channel operation
  103. Endian switch function
  105. Single address mode
  106. Input of DONE* signal
  107. Output of DONE* signal
  111. Interrupt detection
  113. Interrupt status register (ISR)
  114. Interrupt level registers (ILR3-ILR0)
  115. Interrupt mask register (IMR)
  116. SERIAL PORTS (SIO)
  118. Line control register (SLCRn)
  119. Line status register (SLSRn)
  120. DMA/Interrupt control register (SDICRn)
  121. DMA/Interrupt status register (SDISRn)
  122. FIFO control register (SFCRn)
  123. Baudrate control register (SBGRn)
  124. Transmit FIFO buffer (TFIFOn)
  126. Serial clock generator
  127. Receiver Controller
  128. Hand shake function
  129. Parity control
  130. Timing Explanations
  131. Operation at the time of receiving (8 and 9 bit length multi-controller system
  133. Transmit halt timing by CTS
  134. TIMERS/COUNTERS
  136. Watchdog timer mode register 2 (WTMR2)
  138. Pulse generator mode
  139. Watchdog timer mode
  141. Pulse generator mode F/F output timing
  142. IO PORTS (PIO)
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