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Samsung S5PC110 manuals

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S5PC110

Brand: Samsung | Category: Computer Hardware
Table of contents
  1. important notice
  2. revision history
  3. Table of Contents
  4. Table Of Contents
  5. Architectural Overview
  6. Figure 1-1 S5PC110 Block Diagram
  7. Microprocessor
  8. Memory Subsystem
  9. Multimedia
  10. Audio Subsystem
  11. Connectivity
  12. System Peripheral
  13. Conventions
  14. Memory Map
  15. Memory Address Map
  16. CHIPID
  17. Table of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Overview of CHIP ID
  25. Register Description
  26. General Purpose Input/ Output
  27. Features
  28. IO Driver strength
  29. Input/ Output Description
  31. Port Group GPA0 Control Register
  32. Port Group GPA1 Control Register
  33. Port Group GPB Control Register
  34. Port Group GPC0 Control Register
  35. Port Group GPC1 Control Register
  36. Port Group GPD0 Control Register
  37. Port Group GPD1 Control Register
  38. Port Group GPE0 Control Register
  39. Port Group GPE1 Control Register
  40. Port Group GPF0 Control Register
  41. Port Group GPF1 Control Register
  42. Port Group GPF2 Control Register
  43. Port Group GPF3 Control Register
  44. Port Group GPG0 Control Register
  45. Port Group GPG1 Control Register
  46. Port Group GPG2 Control Register
  47. Port Group GPG3 Control Register
  48. Port Group GPI Control Register
  49. Port Group GPJ0 Control Register
  50. Port Group GPJ1 Control Register
  51. Port Group GPJ2 Control Register
  52. Port Group GPJ3 Control Register
  53. Port Group GPJ4 Control Register
  54. Port Group MP0_1 Control Register
  55. Port Group MP0_2 Control Register
  56. Port Group MP0_3 Control Register
  57. Port Group MP0_4 Control Register
  58. Port Group MP0_5 Control Register
  59. Port Group MP0_6 Control Register
  60. Port Group MP0_7 Control Register
  61. Port Group MP1_0 Control Register
  62. Port Group MP1_2 Control Register
  63. Port Group MP1_4 Control Register
  64. Port Group MP1_6 Control Register
  65. Port Group MP1_8 Control Register
  66. Port Group MP2_1 Control Register
  67. Port Group MP2_3 Control Register
  68. Port Group MP2_5 Control Register
  69. Port Group MP2_7 Control Register
  70. Port Group ETC0 Control Register
  71. Port Group ETC1 Control Register
  72. Port Group ETC2 Control Register
  73. Port Group ETC3 is reserved
  74. GPIO Interrupt Control Registers
  75. Port Group GPH0 Control Register
  76. Port Group GPH1 Control Register
  77. Port Group GPH2 Control Register
  78. Port Group GPH3 Control Register
  79. External Interrupt Control Registers
  80. Extern Pin Configuration Registers in Power down Mode
  81. Clock Controller
  82. Clock Declaration
  83. Clocks from CMU
  84. Clock Relationship
  85. Recommended PLL PMS Value for APLL
  86. Recommended PLL PMS Value for MPLL
  87. Recommended PLL PMS Value for VPLL
  88. Clock Generation
  89. Table 3-5 Maximum Operating Frequency for Each Sub-block
  90. Clock Configuration Procedure
  91. Special Clock Description
  92. Table 3-7 I/O Clocks in S5PC110
  94. PLL Control Registers
  95. Clock Source Control Registers
  96. Clock Divider Control Register
  97. Clock Gating Control Register
  98. Clock Output Configuration Register
  99. Figure 3-4 CLKOUT Waveform with DCLK Divider
  100. Clock Divider Status SFRs
  101. Clock MUX Status SFRs
  102. Other SFRs
  103. Miscellaneous SFRs
  104. Power Management
  105. FunctionAL Description of PMU
  106. Table 4-2 S5PC110 Power Domains of Internal Logic
  107. System Power Mode
  108. Normal Mode
  109. IDLE Mode
  110. STOP Mode
  111. DEEP-STOP Mode
  112. SLEEP Mode
  113. System Power Mode Transition
  114. Figure 4-2 Internal Operation During Power Mode Transition
  115. Transition Entering/ Exiting Condition
  116. Cortex-A8 Power Mode
  117. Figure 4-3 Cortex-A8 Power Mode Transition Diagram
  118. State Save and Restore
  119. Wakeup Sources
  120. External Power Control
  121. USB OTG PHY
  122. MIPI D-PHY
  123. Table 4-8 The Status of MPLL and SYSCLK After Wake-Up
  124. ADC I/O
  125. Internal memory control
  126. Reset Control
  127. Table 4-10 Register Initialization Due to Various Resets
  129. Clock Control Register
  130. Reset Control Register
  131. Power Management Register
  132. MISC Register
  133. Intelligent Energy Management
  134. Key Features of Intelligent Energy Management
  135. Block Diagram
  136. Functional Description of Intelligent Energy Management
  137. IEM System Operation
  138. IEM Implementation and Driver Setting
  139. HPM Structure and Closed-Loop Behavior
  140. Figure 5-5 IEM Closed-Loop Control Flow in APC1 HPM Delay
  141. Figure 5-6 HPM Delay Tap structure in S5PC110
  142. Initialization Sequence
  143. I/O Description
  145. IEC Related Registers
  146. APC1 Related Registers
  147. BOOTING SEQUENCE
  148. Figure 6-1 Block Diagram of Booting Time Operation
  149. Scenario Description
  150. Booting Sequence Example
  151. Fixed PLL and Clock Setting
  152. OM Pin Configuration
  153. Secure Booting
  154. Figure 6-3 Secure Booting Diagram
  155. bus configuration
  156. dma controller
  157. pwm operation
  158. watchdog timer
  159. modes of operation
  160. register map
  161. address mapping
  162. camera interface
  163. external interface
  164. data format
  165. hardware overview
  166. data flow
  167. video dac
  168. block diagram of audio subsystem
  169. electrical data
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