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Samsung S3C2416 manuals
S3C2416
Table of contents
- important notice
- revision history
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
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- Table Of Contents
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- Table Of Contents
- Table Of Contents
- Table Of Contents
- Introduction
- Features
- Block Diagram
- Pin Assignments
- Signal Descriptions
- Memory Map
- Base Address of Special Registers
- Overview
- Functional Descriptions
- Watchdog Reset
- Software Reset
- Clock Management
- Main Oscillator Circuit Examples
- PLL (Phase-Locked-Loop)
- System Clock Control
- ARM & BUS Clock Divide Ratio
- Examples for configuring clock regiter to produce specific frequency of AMBA clocks
- ESYSCLK Control
- Power Management
- Power Saving Modes
- Entering STOP Mode and Exiting STOP Mode (wake-up)
- Entering SLEEP Mode and Exiting SLEEP Mode (wake-up)
- Wake-Up Event
- Power Saving Mode Entering/Exiting Condition
- Register Descriptions
- Individual Register Descriptions
- Clock Control Register (CLKSRC, CLKDIV, HCLKCON, PCLKCON, and SCLKCON)
- Power Management Registers (PWRMODE and PWRCFG)
- Reset Control Registers (SWRST and RSTCON)
- Control of retention PAD(I/O) when normal mode and wake-up from sleep mode
- System Controller Status Registers (WKUPSTAT and RSTSTAT)
- Bus Configuration Register (BUSPRI0, BUSPRI1, and BUSMISC)
- Information Register 0,1,2,3
- USB PHY Control register (PHYCTRL)
- USB PHY Power Control Register (PHYPWR)
- USB Clock Control Register (UCLKCON)
- Special Function Registers
- EBI Control Register (EBICON)
- Bus Priority MAP
- Feature
- Asynchronous Read
- Read Timing Diagram (DRnCS = 1, DRnOWE = 1)
- Asynchronous Burst Read
- Synchronous Read/Synchronous Burst Read
- Asynchronous Write
- Write Timing Diagram (DRnCS = 1, DRnOWE = 0)
- Synchronous Write/ Synchronous Burst Write
- Bus Turnaround
- Memory Interface with 8-bit SRAM (2MB)
- Special Registers
- Bank Write Wait State Control Registers 0-5
- Bank Write Enable Assertion Delay Control Registers 0-5
- Bank Control Registers 0-5
- Bank Onenand Type Selection Register
- SMC Control Register
- Mobile DRAM Initialization Sequence
- Memory Interface with 16-bit SDRAM (4Mx16, 4banks)
- Memory Interface with 16-bit Mobile DDR and DDR2
- DRAM Timing Diagram
- t ARFC Timing Diagram
- Mobile DRAM Configuration Register
- Mobile DRAM Control Register
- Mobile DRAM Timming Control Register
- Mobile DRAM (Extended ) Mode RegiSter Set Register
- Mobile DRAM Refresh Control Register
- GPC5/6/7 Pin Configuration Table in IROM Boot Mode
- NAND Flash Access
- Data Register Configuration
- bit ECC Programming Encoding and Decoding
- bit ECC Programming Guide (DECODING)
- Memory Mapping(NAND boot and Other boot)
- NAND Flash Memory Configuration
- NAND Flash Controller Special Registers
- Nand Flash Configuration Register
- Control Register
- Command Register
- Main Data area ECC Register
- Progrmmable Block Address Register
- Softlock and Lock-tight
- NFCON Status Register
- ECC0/1 Error Status Register
- Main Data Area ECC0 Status Register
- Spare Area ECC Status Register
- ECC 0/1/2 for 8bit ECC Status Register
- bit ECC Main Data ECC 0/1/2/3 Status Register
- bit ECC Error Pattern Register
- DMA Request Sources
- DMA Operation
- External DMA Dreq/Dack Protocol
- Demand/Handshake Mode Comparison
- Burst 4 Transfer size
- Examples of Possible Cases
- DMA Special Registers
- DMA Initial Source Control Register (DISRCC)
- DMA Initial Destination Register (DIDST)
- DMA Initial Destination Control Register (DIDSTC)
- DMA Control Register (DCON)
- DMA Status Register (DSTAT)
- DMA Current Source Register (DCSRC)
- DMA Mask Trigger Register (DMASKTRIG)
- DMA Requeset Selection Register (DMAREQSEL)
- Interrupt Group Multiplexing Diagram
- Interrupt Controller Operation
- Interrupt Sources
- Interrupt Priority Generating Block
- Interrupt Priority
- Interrupt Controller Special Registers
- Source Pending (SRCPND) Register
- Interrupt Mode (INTMOD) Register
- Interrupt Mask (INTMSK) Register
- Interrupt Pending (INTPND) Register
- Interrupt Offset (INTOFFSET) Register
- Sub Source Pending (SUBSRCPND) Register
- Interrupt Sub Mask (INTSUBMSK) Register
- Priority Mode Register (priority_MODE)
- Priority Update Register (priority_UPDATE)
- Port Data Register (GPADAT-GPMDAT)
- I/O Port Control Register
- PORT B Control Registers (GPBCON, GPBDAT, GPBUDP, GPBSEL)
- PORT C Control Registers (GPCCON, GPCDAT, GPCUDP)
- PORT D Control Registers (GPDCON, GPDDAT, GPDUDP)
- PORT E Control Registers (GPECON, GPEDAT, GPEUDP, GPESEL)
- PORT F Control Registers (GPFCON, GPFDAT, GPFUDP)
- PORT G Control Registers (GPGCON, GPGDAT, GPGUDP)
- PORT H Control Registers (GPHCON, GPHDAT, GPHUDP)
- PORT K Control Registers (GPKCON, GPKDAT, GPKUDP)
- PORT L Control Registers (GPLCON, GPLDAT, GPLUDP, GPLSEL)
- PORT M Control Registers (GPMCON, GPMDAT, GPMUDP)
- Miscellaneous Control Register (MISCCR)
- DCLK Control Registers (DCLKCON)
- EXTINTn (External Interrupt Control Register n)
- EINTMASK (External Interrupt Mask Register)
- EINTPEND (External Interrupt Pending Register)
- GSTATUSn (General Status Registers)
- DSCn (Drive Strength Control)
- PDDMCON (Power Down SDRAM Control Register)
- PDSMCON (Power Down SRAM Control Register)
- GPIO Alive & Sleep Part
- Watchdog Timer Operation
- Consideration of Debugging Environment
- Watchdog Timer Special Registers
- Watchdog Timer Data (WTDAT) Register
- bit PWM Timer Block Diagram
- PWM Timer Operation
- Basic Timer Operation
- Auto Reload & Double Buffering
- Timer Initialization Using Manual Update Bit and Inverter Bit
- Timer Operation
- Pulse Width Modulation (PWM)
- Output Level Control
- DEAD Zone Generator
- DMA Request Mode
- PWM Timer Control Registers
- Timer Configuration Register1 (TCFG1)
- Timer Control (TCON) Register
- Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)
- Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)
- Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)
- Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)
- Timer 4 Count Buffer Register (TCNTB4)
- Real Time Clock Operation Description
- RTC Tick Interrupt Clock Scheme
- External Interface
- Register Description
- UART Operation
- UART AFC Interface
- Interrupts in Connection with FIFO
- Example showing UART Receiving 5 Characters with 2 Errors
- IrDA Function Block Diagram
- Serial I/O Frame Timing Diagram (Normal UART)
- Clock, EPLL Speed Guide
- UART Special Registers
- UART Control Register
- UART FIFO Control Register
- UART Modem Control Register
- UART Tx/Rx Status Register
- UART Error Status Register
- UART FIFO Status Register
- UART Modem Status Register
- UART Transmit BUffer register (Holding Register & FIFO Register)
- UART Baud RATE Divisor Register
- UART Dividing Slot Register
- USB Host Controller Block Diagram
- USB Host Controller Special Registers
- To Activate USB Port1 for USB 2.0 Function
- SIE (Serial Interface Engine)
- USB 2.0 Function Controller Special Registers
- Indexed Registers
- Registers
- Endpoint Interrupt Register (EIR)
- Endpoint Interrupt Enable Register (EIER)
- Function Address Register (FAR)
- ENdpoint Direction Register (EDR)
- Test Register (TR)
- System Status Register (SSR)
- System Control Register (SCR)
- EP0 Status Register (EP0SR)
- EP0 Control Register (EP0CR)
- Endpoint# Buffer Register (EP#BR)
- Endpoint Status Register (ESR)
- Endpoint Control Register (ECR)
- Byte read Count Register (BRCR)
- Byte Write Count Register (BWCR)
- MAX Packet Register (MPR)
- DMA Control Register (DCR)
- DMA Transfer Counter Register (DTCR)
- DMA FIFO Counter Register (DFCR)
- DMA Total Transfer Counter Register 1/2 (DTTCR 1/2)
- DMA Interface Control Register (DICR)
- Memory Base Address Register (MBAR)
- Memory Current Address Register (MCAR)
- AHB Master(DMA) Operation Flow Chart
- IN Transfer Operation Flow
- IIC-Bus Block Diagram
- IIC-Bus Interface
- Data Transfer Format
- ACK Signal Transmission
- Read-Write Operation
- Flowcharts of Operations in Each Mode
- Operations for Master/Receiver Mode
- Operations for Slave/Transmitter Mode
- Operations for Slave/Receiver Mode
- IIC-Bus Interface Special Registers
- Multi-Master IIC-Bus Control/Status (IICSTAT) Register
- Multi-Master IIC-Bus Address (IICADD) Register
- Multi-Master IIC-Bus Line Control(IICLC) Register
- Color Format Conversion
- Command FIFO
- Rendering Pipeline
- Transparent Mode
- Color Expansion
- Rotation
- Rotation Example
- Clipping
- Alpha Blending
- General Registers
- Command Registers
- Parameter Setting Registers
- Operation Mode
- HS_SPI Transfer Format
- Special Function Register Descriptions
- Special Function Register
- Sequence
- SD Clock Supply Sequence
- SD Clock Stop Sequence
- SD Bus Power Control Sequence
- Change Bus Width Sequence
- Timeout Setting for DAT Line
- SD Command Issue Sequence
- Command Complete Sequence
- Transaction Control with Data Transfer Using DAT Line
- Transaction Control with Data Transfer Using DAT Line Sequence (Using DMA)
- Abort Transaction
- SDI Special Registers
- SDMA System Address Register
- Block Size Register
- Block Count Register
- Argument Register
- Transfer Mode Register
- Determination of Transfer Type
- Relation Between Parameters and the Name of Response Type
- Response Register
- Buffer Data Port Register
- Present State Register
- Card Detect State
- Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer
- Host Control Register
- Power Control Register
- Block Gap Control Register
- Wakeup Control Register
- Clock Control Register
- Timeout Control Register
- Software Reset Register
- Normal Interrupt Status Register
- Error Interrupt Status Register
- The relation between Command CRC Error and Command Timeout Error
- Normal Interrupt Status Enable Register
- Error Interrupt Status Enable Register
- Normal Interrupt Signal Enable Register
- Error Interrupt Signal Enable Register
- Autocmd12 Error Status Register
- Capabilities Register
- Maximum Current Capabilities Register
- Control Register 2
- Control Register 3
- Debug Register
- Force Event Register for Auto CMD12 Error Status
- Force Event Register for Error Interrupt Status
- ADMA Error Status Register
- ADMA System Address Register
- HOST Controller Version Register
- Functional Description
- Interface
- Overview of the Color Data
- BPP(1+5:5:5, BSWP/HWSWP=0) Display Types
- BPP(5:6:5, BSWP/HWSWP=0) Display Types
- VD signal Connection
- Palette usage
- BPP (A:6:6:6) Palette Data Format
- Window Blending
- Blending Diagram/Details
- Color Key Block Diagram
- Color Key Function Configurations
- Vtime Controller Operation
- Virtual Display
- RGB Interface I/O
- LCD CPU Interface I/O (I80-system I/F)
- LCD Signal Muxing Table (RGB and i-80 I/F)
- Programmer's Model
- ADC & Touch Screen Interface Operation
- Function Descriptions
- Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode
- ADC and Touch Screen Interface Special Registers
- ADC Touch Screen Control (ADCTSC) Register
- ADC Start Delay (ADCDLY) Register
- ADC Conversion Data (ADCDAT0) Register
- ADC Conversion Data (ADCDAT1) Register
- ADC Channel Mux Register (ADCMUX)
- Master/Slave Mode
- DMA Transfer
- Audio Serial Data Format
- IIS Audio Serial Data Formats
- Sampling Frequency and Master Clock
- Programming Guide
- Example Code
- TX FIF0 Structure for BLC = 10 (24-bits/channel)
- RX FIF0 Structure for BLC = 10 (24-bits/channel)
- IIS-BUS Interface Special Registers
- IIS Control Register (IISCON)
- IIS Mode Register (IISMOD)
- IIS FIFO Control Register (IISFIC)
- IIS Transmit Register (IISTXD)
- AC97 Controller Operation
- Internal Data Path
- Operation Flow Chart
- AC-link Digital Interface Protocol
- AC-link Output Frame (SDATA_OUT)
- AC-link Input Frame (SDATA_IN)
- AC-link Input Frame
- AC97 Power-Down
- Codec Reset
- AC97 Controller State Diagram
- AC97 Controller Special Registers
- AC97 Global Control Register (AC_GLBCTRL)
- AC97 Global Status Register (AC_GLBSTAT)
- AC97 Codec Status Register (AC_CODEC_STAT)
- AC97 MIC In Channel FIFO Address Register (AC_MICADDR)
- PCM Audio Interface
- PCM Timing
- PCM Input Clock Diagram
- PCM Registers
- PCM Control Register
- PCM CLK Control Register
- The PCM Tx FIFO Register
- PCM Rx FIFO Register
- PCM Interrupt Control Register
- PCM Interrupt Status Register
- PCM FIFO Status Register
- PCM Interrupt Clear Register
- Absolute Maximum Ratings
- Recommended Operating Conditions
- D.C. Electrical Characteristics
- Special Memory DDR I/O PAD DC Electrical Characteristics
- USB DC Electrical Characteristics
- A.C. Electrical Characteristics
- HCLK/CLKOUT/SCLK in case that EXTCLK is used
- Power-On Oscillation Setting Timing
- Sleep Mode Return Oscillation Setting Timing
- SMC Synchronous Read Timing
- SMC Asynchronous Write Timing
- SMC Wait Timing
- Nand Flash Timing
- SDRAM READ / WRITE Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit)
- DDR2 Timing
- SDRAM MRS Timing
- SDRAM Auto Refresh Timing (Trp = 2, Trc = 4)
- External DMA Timing (Handshake, Single transfer)
- IIS Interface Timing (I2S Master Mode Only)
- High Speed SDMMC Interface Timing
- USB Timing (Data signal rise/fall time)
- Clock Timing Constants
- SMC Timing Constants
- Memory Interface Timing Constants (SDRAM)
- DMA Controller Module Signal Timing Constants
- IIS Controller Module Signal Timing Constants(I2S Slave Mode Only)
- High Speed SPI Interface Transmit/Receive Timing Constants
- USB Electrical Specifications
- USB Full Speed Output Buffer Electrical Characteristics
- PCM Interface Timing
- Package Dimensions
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