Epson S1D13706 manuals
S1D13706
Table of contents
- user manual
- Table Of Contents
- Vancouver Design Center
- Introduction
- Features
- Installation and Configuration
- Configuration Jumpers
- CPU Interface
- CPU Bus Connector Pin Mapping
- LCD Interface Pin Mapping
- Technical Description
- Passive/Active LCD Panel Support
- References
- Parts List
- Schematics
- Board Layout
- Technical Support
S1D13706
Table of contents
- Riesstrasse
- hardware functional specification
- Table of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Introduction
- Features
- Display Modes
- Typical System Implementation Diagrams
- figure 3-3: typical system diagram (hitachi sh-4 bus)
- figure 3-5: typical system diagram (mc68k # 1, motorola 16-bit)
- figure 3-7: typical system diagram (motorola redcap2 bus)
- Pinout Diagram - TQFP15 - 100pin
- Pinout Diagram - CFLGA - 104pin
- Pinout Diagram - Die Form
- Pin Descriptions
- LCD Interface
- Clock Input
- Summary of Configuration Options
- Host Bus Interface Pin Mapping
- LCD Interface Pin Mapping
- D.C. Characteristics
- A.C. Characteristics
- Internal Clocks
- CPU Interface Timing
- Generic #2 Interface Timing (e.g. ISA)
- Hitachi SH-4 Interface Timing
- Hitachi SH-3 Interface Timing
- Motorola MC68K #1 Interface Timing (e.g. MC68000)
- Motorola MC68K #2 Interface Timing (e.g. MC68030)
- Motorola REDCAP2 Interface Timing
- LCD Power Sequencing
- Passive/TFT Power-Off Sequence
- Display Interface
- Generic STN Panel Timing
- Issue Date: 01/11/13 Page
- Single Monochrome 4-Bit Panel Timing
- Single Monochrome 8-Bit Panel Timing
- Single Color 4-Bit Panel Timing
- Single Color 8-Bit Panel Timing (Format 1)
- Single Color 8-Bit Panel Timing (Format 2)
- Single Color 16-Bit Panel Timing
- Generic TFT Panel Timing
- Bit TFT Panel Timing
- x160 Sharp 'Direct' HR-TFT Panel Timing (e.g. LQ031B1DDxx)
- x240 sharp 'direct' hr-tft panel timing (e.g. lq039q2ds)
- x240 Epson D-TFD Panel Timing (e.g. LF26SCR)
- x240 Epson D-TFD Panel Timing (e.g. LF37SQR)
- Clocks
- PCLK
- PWMCLK
- Clock Selection
- Clocks versus Functions
- Registers
- Register Descriptions
- Clock Configuration Registers
- Look-Up Table Registers
- Panel Configuration Registers
- Display Mode Registers
- Miscellaneous Registers
- General IO Pins Registers
- Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers
- Frame Rate Calculation
- Display Data Formats
- Look-Up Table Architecture
- Color Modes
- Concept
- Register Programming
- Picture-in-Picture Plus (PIP+)
- with swivelview enabled
- Big-Endian Bus Interface 14.1 Byte Swapping Bus Data
- Bpp Color Depth
- Power Save Mode
- Mechanical Data
- References
- Sales and Technical Support
- programming notes and examples
- Table of Contents
- Table Of Contents
- Table Of Contents
- memory models
- memory organization for two bit-per-pixel (4 colors/gray shades)
- memory organization for 8 bpp (256 colors/64 gray shades)
- look-up table (lut)
- look-up table read registers
- look-up table organization
- gray shade modes
- color modes
- power save mode enable
- enabling power save mode
- enabling the lcd panel
- picture-in-picture plus
- picture-in-picture-plus examples
- identifying the s1d
- hardware abstraction layer (hal)
- general hal support
- advance hal functions
- surface support
- register access
- memory access
- color manipulation
- virtual display
- register/display memory
- porting libse to a new target platform
- building the libse library for sh3 target example
- sample code
- cfg configuration program
- Table of Contents
- Table Of Contents
- cfg configuration tabs
- preferences tab
- clocks tab
- panel tab
- panel power tab
- registers tab
- cfg menus
- save as
- configure multiple
- enable tooltips
- installation guide
- Table of Contents
- Table Of Contents
- list of figures
- installation and configuration
- configuration jumpers
- cpu interface pin mapping
- cpu bus connector pin mapping
- direct host bus interface support
- manual/software adjustable lcd panel negative power supply (vlcd)
- software adjustable lcd backlight intensity support using pwm
- clock synthesizer and clock options
- document sources
- parts list
- board layout
- technical support
- hardware description
- power consumption
- Table of Contents
- Table Of Contents
- interfacing to the mpc
- memory controller module
- user-programmable machine (upm)
- mpc821 to s1d13706 interface
- mpc821ads evaluation board hardware connections
- mpc821 chip select configuration
- Table of Contents
- Table Of Contents
- connecting to the sharp lq039q2ds01 hr-tft
- s1d13706 to lq039q2ds01 pin mapping
- connecting to the sharp lq031b1ddxx hr-tft
- s1d13706 to lq031b1ddxx pin mapping
- sharp hr-tft panel
- Table of Contents
- Table Of Contents
- vddh and vdd - horizontal and vertical analog voltages
- veey - lcd panel drive voltage for vertical power supplies - brightness reference
- vcc - horizontal logic power supply
- swing power supply for the vertical drive (v0y) and logic (vccy / v5y) voltages
- level shift and clamp circuit for vertical logic control signals
- s1d13706 to d-tfd panel pin mapping
- lcd pin mapping for horizontal connector (lf37sqt and lf26sct)
- lcd pin mapping for y connector (lf37sqt)
- lcd pin mapping for y connector (lf26sct)
- power-on/off sequence
- gcp data signal
- programming gcp data