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Epson S1D13706 manuals

S1D13706 first page preview

S1D13706

Brand: Epson | Category: Motherboard
Table of contents
S1D13706 first page preview

S1D13706

Brand: Epson | Category: Controller
Table of contents
  1. Riesstrasse
  2. hardware functional specification
  3. Table of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Introduction
  9. Features
  10. Display Modes
  11. Typical System Implementation Diagrams
  12. figure 3-3: typical system diagram (hitachi sh-4 bus)
  13. figure 3-5: typical system diagram (mc68k # 1, motorola 16-bit)
  14. figure 3-7: typical system diagram (motorola redcap2 bus)
  15. Pinout Diagram - TQFP15 - 100pin
  16. Pinout Diagram - CFLGA - 104pin
  17. Pinout Diagram - Die Form
  18. Pin Descriptions
  19. LCD Interface
  20. Clock Input
  21. Summary of Configuration Options
  22. Host Bus Interface Pin Mapping
  23. LCD Interface Pin Mapping
  24. D.C. Characteristics
  25. A.C. Characteristics
  26. Internal Clocks
  27. CPU Interface Timing
  28. Generic #2 Interface Timing (e.g. ISA)
  29. Hitachi SH-4 Interface Timing
  30. Hitachi SH-3 Interface Timing
  31. Motorola MC68K #1 Interface Timing (e.g. MC68000)
  32. Motorola MC68K #2 Interface Timing (e.g. MC68030)
  33. Motorola REDCAP2 Interface Timing
  34. LCD Power Sequencing
  35. Passive/TFT Power-Off Sequence
  36. Display Interface
  37. Generic STN Panel Timing
  38. Issue Date: 01/11/13 Page
  39. Single Monochrome 4-Bit Panel Timing
  40. Single Monochrome 8-Bit Panel Timing
  41. Single Color 4-Bit Panel Timing
  42. Single Color 8-Bit Panel Timing (Format 1)
  43. Single Color 8-Bit Panel Timing (Format 2)
  44. Single Color 16-Bit Panel Timing
  45. Generic TFT Panel Timing
  46. Bit TFT Panel Timing
  47. x160 Sharp 'Direct' HR-TFT Panel Timing (e.g. LQ031B1DDxx)
  48. x240 sharp 'direct' hr-tft panel timing (e.g. lq039q2ds)
  49. x240 Epson D-TFD Panel Timing (e.g. LF26SCR)
  50. x240 Epson D-TFD Panel Timing (e.g. LF37SQR)
  51. Clocks
  52. PCLK
  53. PWMCLK
  54. Clock Selection
  55. Clocks versus Functions
  56. Registers
  57. Register Descriptions
  58. Clock Configuration Registers
  59. Look-Up Table Registers
  60. Panel Configuration Registers
  61. Display Mode Registers
  62. Miscellaneous Registers
  63. General IO Pins Registers
  64. Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers
  65. Frame Rate Calculation
  66. Display Data Formats
  67. Look-Up Table Architecture
  68. Color Modes
  69. Concept
  70. Register Programming
  71. Picture-in-Picture Plus (PIP+)
  72. with swivelview enabled
  73. Big-Endian Bus Interface 14.1 Byte Swapping Bus Data
  74. Bpp Color Depth
  75. Power Save Mode
  76. Mechanical Data
  77. References
  78. Sales and Technical Support
  79. programming notes and examples
  80. Table of Contents
  81. Table Of Contents
  82. Table Of Contents
  83. memory models
  84. memory organization for two bit-per-pixel (4 colors/gray shades)
  85. memory organization for 8 bpp (256 colors/64 gray shades)
  86. look-up table (lut)
  87. look-up table read registers
  88. look-up table organization
  89. gray shade modes
  90. color modes
  91. power save mode enable
  92. enabling power save mode
  93. enabling the lcd panel
  94. picture-in-picture plus
  95. picture-in-picture-plus examples
  96. identifying the s1d
  97. hardware abstraction layer (hal)
  98. general hal support
  99. advance hal functions
  100. surface support
  101. register access
  102. memory access
  103. color manipulation
  104. virtual display
  105. register/display memory
  106. porting libse to a new target platform
  107. building the libse library for sh3 target example
  108. sample code
  109. cfg configuration program
  110. Table of Contents
  111. Table Of Contents
  112. cfg configuration tabs
  113. preferences tab
  114. clocks tab
  115. panel tab
  116. panel power tab
  117. registers tab
  118. cfg menus
  119. save as
  120. configure multiple
  121. enable tooltips
  122. installation guide
  123. Table of Contents
  124. Table Of Contents
  125. list of figures
  126. installation and configuration
  127. configuration jumpers
  128. cpu interface pin mapping
  129. cpu bus connector pin mapping
  130. direct host bus interface support
  131. manual/software adjustable lcd panel negative power supply (vlcd)
  132. software adjustable lcd backlight intensity support using pwm
  133. clock synthesizer and clock options
  134. document sources
  135. parts list
  136. board layout
  137. technical support
  138. hardware description
  139. power consumption
  140. Table of Contents
  141. Table Of Contents
  142. interfacing to the mpc
  143. memory controller module
  144. user-programmable machine (upm)
  145. mpc821 to s1d13706 interface
  146. mpc821ads evaluation board hardware connections
  147. mpc821 chip select configuration
  148. Table of Contents
  149. Table Of Contents
  150. connecting to the sharp lq039q2ds01 hr-tft
  151. s1d13706 to lq039q2ds01 pin mapping
  152. connecting to the sharp lq031b1ddxx hr-tft
  153. s1d13706 to lq031b1ddxx pin mapping
  154. sharp hr-tft panel
  155. Table of Contents
  156. Table Of Contents
  157. vddh and vdd - horizontal and vertical analog voltages
  158. veey - lcd panel drive voltage for vertical power supplies - brightness reference
  159. vcc - horizontal logic power supply
  160. swing power supply for the vertical drive (v0y) and logic (vccy / v5y) voltages
  161. level shift and clamp circuit for vertical logic control signals
  162. s1d13706 to d-tfd panel pin mapping
  163. lcd pin mapping for horizontal connector (lf37sqt and lf26sct)
  164. lcd pin mapping for y connector (lf37sqt)
  165. lcd pin mapping for y connector (lf26sct)
  166. power-on/off sequence
  167. gcp data signal
  168. programming gcp data
S1D13706 first page preview

S1D13706

Brand: Epson | Category: Motherboard
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