Abov MC96FM204 manuals

MC96FM204

Brand: Abov | Category: Microcontrollers

Table of contents

1. Table Of Contents
2. Table Of Contents
3. Table Of Contents
4. Table Of Contents
5. Table Of Contents
6. Table Of Contents
7. Overview
8. Features
9. Ordering Information
10. Development Tools
11. Figure 1.2 PGMplusUSB (Single Writer)
12. Block Diagram
13. Pin Assignment
14. Figure 3.2 MC96FM204 16SOP/TSSOP Pin Assignment
15. Package Diagram
16. Figure 4.2 20-Pin TSSOP Package
17. Figure 4.3 16-Pin SOP Package
18. Figure 4.4 16-Pin TSSOP Package
19. Pin Description
20. Port Structures
21. External Interrupt I/O Port
22. Electrical Characteristics
23. A/D Converter Characteristics
24. Low Voltage Reset and Low Voltage Indicator Characteristics
25. Analog Comparator Characteristics
26. High Frequency Internal RC Oscillator Characteristics
27. DC Characteristics
28. AC Characteristics
29. SPI Characteristics
30. Data Retention Voltage in Stop Mode
31. Internal Flash Rom Characteristics
32. Main Clock Oscillator Characteristics
33. Main Oscillation Stabilization Characteristics
34. Recommended Circuit and Layout
35. Recommended Circuit and Layout with SMPS Power
36. Typical Characteristics
37. Figure 7.13 RUN (IDD1, LFIRC=250kHz) Current
38. Figure 7.15 IDLE (IDD2, HFIRC =8MHz) Current
39. Figure 7.17 STOP (IDD5, XIN=8MHz) Current
40. Memory
41. Figure 8.1 Program Memory
42. Data Memory
43. Figure 8.3 Lower 128 Bytes RAM
44. Table 8-1 SFR Map Summary
45. Table 8-2 SFR Map
46. I/O Ports
47. Table 9-1 Port Register Map
48. Interrupt Controller
49. External Interrupt
51. Interrupt Vector Table
52. Figure 10.3 Interrupt Vector Address Table
53. Effective Timing after Controlling Interrupt Bit
54. Multi Interrupt
55. Interrupt Enable Accept Timing
56. Interrupt Timing
57. Interrupt Register Description
58. Peripheral Hardware
59. Table 11-1 Clock Generator Register Map
60. Basic Interval Timer
61. Table 11-2 Basic Interval Timer Register Map
62. Watch Dog Timer
63. Figure 11.4 Watch Dog Timer Block Diagram
64. Timer 0
65. Figure 11.6 8-Bit Timer/Counter 0 Example
66. Figure 11.7 8-Bit Timer 0 Block Diagram
67. Table 11-4 Timer 0 Register Map
68. Timer 1
69. Figure 11.8 16-Bit Timer/Counter Mode for Timer 1
70. Figure 11.10 16-Bit Capture Mode for Timer 1
71. Figure 11.11 Input Capture Mode Operation for Timer 1
72. Figure 11.13 16-Bit PPG Mode for Timer 1
73. Figure 11.14 16-Bit PPG Mode Timming chart for Timer 1
74. Figure 11.15 16-Bit Timer 1 Block Diagram
75. Timer 2
76. Figure 11.16 16-Bit Timer/Counter Mode for Timer 2
77. Figure 11.18 16-Bit Capture Mode for Timer 2
78. Figure 11.19 Input Capture Mode Operation for Timer 2
79. Figure 11.21 16-Bit PPG Mode for Timer 2
80. Figure 11.22 16-Bit PPG Mode Timming chart for Timer 2
81. Figure 11.23 16-Bit Timer 2 Block Diagram
82. Buzzer Driver
83. Table 11-10 Buzzer Driver Register Map
84. Figure 11.25 SIO Block Diagram
85. Table 11-11 SPI Register Map
86. Bit A/D Converter
87. Figure 11.28 8-bit ADC Block Diagram
88. Figure 11.30 A/D Converter Operation Flow
89. Analog Comparator
90. Table 11-13 ADC Register Map
91. Operational Amplifier
92. Table 11-14 Operational Amplifier Register Map
93. Power Down Operation
94. IDLE Mode
95. STOP Mode
96. Release Operation of STOP Mode
97. Table 12-2 Power Down Operation Register Map
98. RESET
99. RESET Noise Canceller
100. Figure 13.5 Configuration Timing when Power-on
101. Table 13-2 Boot Process Description
102. External RESETB Input
103. Brown Out Detector Processor
104. LVI Block Diagram
105. Table 13-3 Reset Operation Register Map
106. On-chip Debug System
107. Two-Pin External Interface
108. Figure 14.2 10-bit Transmission Packet
109. Figure 14.4 Bit Transfer on the Serial Bus
110. Figure 14.6 Acknowledge on the Serial Bus
111. Figure 14.8 Connection of Transmission
112. Flash Memory
113. Figure 15.1 Flash Program ROM Structure
114. Table 15-1 Flash Memory Register Map
115. Figure 15.2 Flow of Protection for Invalid Erase/Write
116. Configure Option
117. APPENDIX