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Fujitsu MB90428A manuals

MB90428A first page preview

MB90428A

Brand: Fujitsu | Category: Microcontrollers
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Overview of Product
  22. Features
  23. Block Diagram
  24. Package Dimension
  25. Fig. 1.3 Package Dimension (LQFP100)
  26. Pin Assignment
  27. Fig. 1.5 Pin Assignment (LQFP100)
  28. Pin Description
  29. I/O Circuits
  30. Notes on Handling Devices
  31. Fig. 1.6 Example of using external clock
  32. Fig. 1.8 Undefined-value Output Timing Chart
  33. Chapter 2 CPU
  34. Memory Space
  35. Memory Map
  36. Addressing
  37. Linear Type Addressing
  38. Bank Type Addressing
  39. Fig. 2.6 Example of Bank Type Addressing
  40. Allocation of Multi-byte Length Data on Memory
  41. Fig. 2.9 Storage of Multi-byte Length Data in Stack
  42. Register
  43. Dedicated Registers
  44. Table 2-3 Initial Values of Dedicated Registers
  45. Accumulator (A)
  46. Fig. 2.16 Example of 32-bit Data Transfer to Accumulator (A) (register indirect)
  47. Stack Pointer (USP, SSP)
  48. Fig. 2.18 Stack Operation Instructions and Stack Pointers
  49. Processor Status (PS)
  50. Condition Code Register (PS: CCR)
  51. Register Bank Pointer (PS: RP)
  52. Interrupt Level Mask Register (PS: ILM)
  53. Program Counter (PC)
  54. Direct Page Register (DPR)
  55. Bank Register (PCB, DTB, USB, SSB, and ADB)
  56. General-purpose Register
  57. Table 2-6 Typical Function of the General-Purpose Register
  58. Prefix Codes
  59. Bank Select Prefix (PCB, DTB, ADB, and SPB)
  60. Common Register Bank Prefix (CMR)
  61. Flag Change Inhibit Prefix (NCC)
  62. Restrictions on Prefix Code
  63. Fig. 2.29 Interrupt/hold Inhibition Instruction and Prefix Code
  64. Chapter 3 Reset
  65. Overview of Reset
  66. Reset Factors and Oscillation Stabilization Wait Time
  67. Table 3-3 Oscillation Stabilization Wait Time Based on Setting of Clock Selection Register (CKSCR)
  68. External Reset Pin
  69. Reset Operation
  70. Fig. 3.6 Transfer of Reset Vectors and Mode Data
  71. Reset Factor Bit
  72. Fig. 3.8 Configuration of Reset Factor Bit (Watchdog Timer Control Register)
  73. State of Each Pin at Reset
  74. Chapter 4 Clock
  75. Overview of Clock
  76. Fig. 4.1 Clock Supply Map
  77. Block Diagram of Clock Generation Section
  78. Clock Select Register (CKSCR)
  79. Table 4-1 Function of Each Bit of Clock Select Register (CKSCR)
  80. Clock Mode
  81. Fig. 4.3 Transition Diagram of Machine Clock Selection State
  82. Oscillation Stabilization Wait Time
  83. Connection of Oscillator and External Clock
  84. Chapter 5 Low-Power Consumption Mode
  85. Overview of Low-power Consumption Mode
  86. Block Diagram of Low-power Consumption Controller
  87. Low-power Consumption Mode Control Register (LPMCR)
  88. Table 5-1 Function of Each Bit of Low -pow er Consum ption M ode Control Register (LPM CR)
  89. Table 5-2 Instructions At Transition To Low-power Consumption Mode
  90. CPU Intermittent Operation Mode
  91. Standby Mode
  92. Sleep Mode
  93. Fig. 5.5 Cancellation of Sleep Mode by Interrupt
  94. Time-base Timer Mode
  95. Timer Mode
  96. Fig. 5.6 Cancellation of Timer Mode (External Reset)
  97. Stop Mode
  98. Fig. 5.7 Cancellation of Stop Mode (External Reset)
  99. State Transition Diagram
  100. Table 5-4 Operation State in Low-power Consumption Mode
  101. Pin State in Standby Mode, at Reset
  102. Precautions at Using Low-power Consumption Mode
  103. Chapter 6 Interrupt
  104. Overview of Interrupt
  105. Fig. 6.1 General Flow of Interrupt Operation
  106. Interrupt Factor and Interrupt Vector
  107. Interrupt Control Registers and Resources
  108. Interrupt Control Register (ICR00 to ICR15)
  109. Fig. 6.3 Interrupt Control Register (ICR00 to ICR15) at Reading
  110. Function of Interrupt Control Register
  111. Table 6-4 Relationship between Interrupt Level Setting Bits and Interrupt Levels
  112. Hardware Interrupt
  113. Fig. 6.5 Hardw are Interrupt Request during W riting to the Resource Control Register Area
  114. Operation of Hardware Interrupt
  115. Fig. 6.6 Operation of Hardware Interrupt
  116. Processing at Interrupt Operation
  117. Use Procedure for Hardware Interrupt
  118. Multiple Interrupts
  119. Hardware Interrupt Handling Time
  120. Software Interrupt
  121. Fig. 6.11 Operation of Software Interrupt
  122. EI 2 OS Descriptor (ISD)
  123. Table 6-10 Correspondence between Channel Number and Descriptor Address
  124. Fig. 6.14 Configuration of Data Counter (DCT)
  125. Fig. 6.17 Configuration of Buffer Address Pointer (BAP)
  126. Use Procedure for EI 2 OS
  127. Table 6-13 Compensation Value (Z) for Interrupt Handling Time
  128. Exception Handling Interrupt
  129. Stack Operation for Interrupt Handling
  130. Fig. 6.21 Stack Area
  131. Program Example for Interrupt Handling
  132. Chapter 7 Mode Setting
  133. Mode Setting
  134. Mode Pins (MD2 to MD0)
  135. Mode Data
  136. Fig. 7.3 Relationship betw een Access Areas and P hysical Addresses in Single-chip M ode
  137. Chapter 8 I/O Port
  138. Overview of I/O Port
  139. Table 8-1 List of Each Port Functions
  140. Registers and Assignment of Pins Serving as External Pins
  141. Port
  142. Fig. 8.1 Block Diagram of Pins of Port 0
  143. Registers for Port 0 (PDR0, DDR0)
  144. Operation of Port 0
  145. Table 8-6 State of Port 0 Pins
  147. Fig. 8.2 Block Diagram of Pins of Port 1
  148. Registers for Port 1 (PDR1, DDR1)
  149. Operation of Port 1
  150. Table 8-10 State of Port 1 Pins
  152. Fig. 8.3 Block Diagram of Pins of Port 3
  153. Registers for Port 3 (PDR3, DDR3)
  154. Operation of Port 3
  155. Table 8-14 State of Port 3 Pins
  157. Fig. 8.4 Block Diagram of Pins of Port 4
  158. Registers for Port 4 (PDR4, DDR4)
  159. Operation of Port 4
  160. Table 8-18 State of Port 4 Pins
  162. Fig. 8.5 Block Diagram of Pins of Port 5
  163. Registers for Port 5 (PDR5, DDR5)
  164. Operation of Port 5
  165. Table 8-22 State of Port 5 Pins
  167. Fig. 8.6 Block Diagram of Pins of Port 6
  168. Registers for Port 6 (PDR6, DDR6)
  169. Operation of Port 6
  170. Table 8-26 State of Port 6 Pins
  172. Fig. 8.7 Block Diagram of Pins of Port 7
  173. Registers for Port 7 (PDR7, DDR7)
  174. Operation of Port 7
  175. Table 8-30 State of Port 7 Pins
  177. Fig. 8.8 Block Diagram of Pins of Port 8
  178. Registers for Port 8 (PDR8, DDR8)
  179. Operation of Port 8
  180. Table 8-34 State of Port 8 Pins
  182. Fig. 8.9 Block Diagram of Pins of Port 9
  183. Registers for Port 9 (PDR9, DDR9)
  184. Operation of Port 9
  185. Table 8-38 State of Port 9 Pins
  186. Program Example Using I/O Ports
  187. Chapter 9 Watchdog Timer/Time-base Timer/Watch Timer (Sub-Clock)
  188. Block Diagram of Watchdog Timer, Time-base Timer, and Watch Timer
  189. List of Watchdog Timer, Time-base Timer, and Watch Timer Registers
  190. Watchdog Timer Control Register (WDTC)
  191. Table 9-2 WT1 and 0 (Interval Time Select Bits)
  192. Time-base Timer Control Register (TBTC)
  193. Watch timer control register (WTC)
  194. Table 9-4 Selection of Watch Timer Interval
  195. Operation of Watchdog Timer, Time-base Timer, and Watch Timer
  196. Operation of Watchdog Timer
  197. Fig. 9.6 Clearing Timing and Watchdog Timer Interval Time
  198. Operation of Time-base Timer
  199. Table 9-6 Time-base Timer Counter Clear and Oscillation Stabilization Wait Time
  200. Operation of Watch Timer
  201. Precautions at Using Watchdog Timer and Time-base Timer
  202. Fig. 9.7 Operation of Time-base Timer
  203. Program Examples of Watchdog Timer and Time-base Timer
  204. Chapter 10 16-bit Reload Timer
  205. Overview of 16-bit Reload Timer
  206. Table 10-2 Interval Time of 16-bit Reload Timer
  207. Configuration of 16-bit Reload Timer
  208. Pins of 16-bit Reload Timer
  209. Registers for 16-bit Reload Timer
  210. Timer Control Status Register (upper) (TMCSR0/1H)
  211. Table 10-5 Function of Each Bit of Timer Control Status Register (upper TMCSR0, TMCSR1: H)
  212. Timer Control Status Register (lower) (TMCSR0/1L)
  213. Table 10-6 Function of Each Bit of Timer Control Status Register (lower) (TMCSR0/1L)
  214. bit Timer Register (TMR0/1)
  215. bit Reload Register (TMRLR0/1L, TMRLR0/1H)
  216. Interrupt of 16-bit Reload Timer
  217. Operation of 16-bit Reload Timer
  218. Fig. 10.10 State Transition Diagram of Counter
  219. Internal Clock Mode (Reload Mode)
  220. Fig. 10.12 Count Operation in Reload Mode (Operation of External Trigger)
  221. Internal Clock Mode (One-shot Mode)
  222. Fig. 10.15 Count Operation in One-shot Mode (Operation of External Trigger)
  223. Event Count Mode
  224. Fig. 10.18 Count Operation in One-shot Mode (Operation of Event Count Mode)
  225. Precautions at Using 16-bit Reload Timer
  226. Program Example of 16-bit Reload Timer
  227. Chapter 11 Input Capture
  228. Overview of Input Capture
  229. Block Diagram of Input Capture
  230. List of Input Capture Registers
  231. Detailed Explanation of Registers for Input Capture
  232. Detailed Explanation of Registers for 16-bit Free-run Timer
  233. Explanation of Operation
  234. bit Input Capture
  235. bit Free-run Timer
  236. Fig. 11.6 Clearing Timing of 16-bit Free-run Timer
  237. Chapter 12 UART
  238. Overview of UART
  239. Table 12-2 Operation Mode of UART
  240. Configuration of UART
  241. Fig. 12.1 Block Diagram of UART
  242. Pin of UART
  243. Registers for UART
  244. Control Register (SCR0/1)
  245. Table 12-5 Function of Each Bit of Control Register (SCR0/1)
  246. Mode Register (SMR0/1)
  247. Table 12-6 Function of Each Bit of Mode Register (SMR0/1)
  248. Status Register (SSR0/1)
  249. Table 12-7 Function of Each Bit of Status Register (SSR0/1)
  250. Input-Data Register (SIDR0/1) and Output-Data Register (SODR0/1)
  251. Communication Prescaler Control Register (CDCR0/1)
  252. Interrupt of UART
  253. Generation of Receive Interrupt and Timing of Flag Set
  254. Generation of Transmit Interrupt and Timing of Flag Set
  255. Baud Rate of UART
  256. Fig. 12.11 UART Baud Rate Selector
  257. Baud Rate by Dedicated Baud Rate Generator
  258. Table 12-13 Selection of Division Ratio to Obtain Asynchronous Baud Rate
  259. Baud Rate by Internal Timer (16-bit Reload Timer)
  260. Baud Rate by External Clock
  261. Operation of UART
  262. Operation in Asynchronous Mode (Operation Mode 0 or 1)
  263. Fig. 12.15 Transmit Data when Parity Enabled
  264. Operation in Synchronous Mode (Operation Mode 2)
  265. Bidirectional Communication Function (Normal Mode)
  266. Fig. 12.19 Example of Bidirectional Communication Flow
  267. Master/Slave Mode Communication Function (Multiprocessor Mode)
  268. Table 12-16 Selection of Master/Slave Mode Communication Function
  269. Fig. 12.22 Flowchart of Master/Slave Mode Communications
  270. Precautions at Using UART
  271. Program Example of UART
  272. Chapter 13 PPG Timer
  273. Overview of PPG Timer
  274. Block Diagram of PPG Timer
  275. Registers for PPG Timer
  276. Detailed Explanation of Registers for PPG Timer
  277. Operation of PPG Timer
  278. One-shot Operation
  279. Interrupt Factors and Timing
  280. Chapter 14 LCD Controller/Driver
  281. Overview of LCD Controller/Driver
  282. Configuration of LCD Controller/Driver
  283. Internal Split Resistors of LCD Controller/Driver
  284. Fig. 14.3 State when Internal Split Resistors Used
  285. External Split Resistors for LCD Controller/Driver
  286. Fig. 14.6 State when External Split Resistors Used
  287. LCD Controller/Driver Pins
  288. Fig. 14.7 Block Diagram of Pins Related to LCD Controller/Driver
  289. LCD Controller/Driver Registers
  290. LCDC Control Register Lower (LCRL)
  291. Table 14-3 Function of Each Bit of LCDC Control Register Lower (LCRL)
  292. LCDC Control Register Higher (LCRH)
  293. LCD Controller/Driver Display RAM
  294. Table 14-6 Relationship between Duty, Common Output Pins, and Display RAM Bits
  295. Explanation of Operation of LCD Controller/Driver
  296. Output Waveform (1/2 duty) during Operation of LCD Controller/Driver
  297. Fig. 14.13 Example of Output Waveform on 1/2 Bias and 1/2 Duty
  298. Fig. 14.14 Example of LCD Panel Display Data
  299. Output Waveform (1/3 duty) during Operation of LCD Controller/Driver
  300. Fig. 14.15 Example of Output Waveform on 1/3 Bias and 1/3 Duty
  301. Fig. 14.16 Example of LCD Panel Display Data
  302. Output Waveform (1/4 duty) during Operation of LCD Controller/Driver
  303. Fig. 14.17 Example of Output Waveform on 1/3 Bias and 1/4 Duty
  304. Fig. 14.18 Example of LCD Panel Display Data
  305. Chapter 15 Stepping Motor Controller
  306. Fig. 15.1 Block Diagram of Stepping Motor Controller
  307. Stepping Motor Controller Registers
  308. PWM Control Register
  309. PWM1&2 Compare Registers
  310. PWM 1&2 Select Registers
  311. Explanation of Operation of Stepping Motor Controller
  312. Fig. 15.3 Example of PWM 1, 2 Waveform Output
  313. Precautions at Using Stepping Motor Controller
  314. Chapter 16 DTP/External Interrupt Circuit
  315. Overview of DTP/External Interrupt Circuit
  316. Configuration of DTP/External Interrupt Circuit
  317. Pins of DTP/External Interrupt Circuit
  318. Registers for DTP/External Interrupt Circuit
  319. DTP/Interrupt Enable Register (ENIR)
  320. Request Level Setting Register (ELVR)
  321. Explanation of DTP/External Interrupt Circuit Operation
  322. Fig. 16.8 Operation of DTP/External Interrupt Circuit
  323. External Interrupt Function
  324. DTP Function
  325. Precautions at Using DTP/External Interrupt Circuit
  326. Sample Programs for DTP/External Interrupt Circuit
  327. Chapter 17 Delayed Interrupt Generate Module
  328. Overview of Delayed Interrupt Generate Module
  329. Operation of Delayed Interrupt Generate Module
  330. Chapter 18 Timepiece Timer
  331. Overview of Timepiece Timer
  332. Timepiece Timer Registers
  333. Timepiece Timer Control Register
  334. Sub-second Data Register
  335. Second/Minute/Hour Data Register
  336. Chapter 19 8-/10- bit A/D Converter
  337. Overview of 8-/10-bit A/D Converter
  338. Configuration of 8-/10-bit A/D Converter
  339. Pins of 8-/10-bit A/D Converter
  340. Fig. 19.2 Block Diagram of P60/AN0 to P67/AN7 Pins
  341. Registers for 8-/10-bit A/D Converter
  342. A/D Control Status Register Upper (ADCSH)
  343. Table 19-4 Function of Each Bit of A/D Control Status Register Higher (ADCSH)
  344. A/D Control Status Register Lower (ADCSL)
  345. Table 19-5 Function of Each Bit of A/D Control Status Register Lower (ADCSL)
  346. A/D Data Register (ADCRH/ ADCRL)
  347. Table 19-6 Function of Each Bit of A/D Data Register (ADCR)
  348. Interrupt of 8-/10-bit A/D Converter
  349. Explanation of 8-/10-bit A/D Converter Operation
  350. Fig. 19.8 Setting in Continuous Conversion Mode
  351. Fig. 19.9 Setting in Pause-conversion Mode
  352. A/D-converted Data Protection Function
  353. Precautions at Using 8-/10-bit A/D Converter
  354. Chapter 20 Sound Generator
  355. Overview of Sound Generator
  356. Sound Generator Registers
  357. Sound Control Register
  358. Frequency Data Register
  359. Amplitude Data Register
  360. Decrement Grade Register
  361. Chapter 21 ROM Correction
  362. Overview of ROM Correction
  363. Application Example of ROM Correction
  364. Correction Example of Program Errors
  365. Example of Correction Processing
  366. Fig. 21.5 ROM Correction Processing Flow Diagram
  367. Chapter 22 ROM Mirror Function Select Module
  368. Overview of ROM Mirror Function Select Module
  369. ROM Mirror Function Select Register (ROMM)
  370. Chapter 23 Can Controller
  371. Features of CAN Controller
  372. Block Diagram of CAN Controller
  373. List of Overall Control Registers
  374. Table 23-2 List of CAN WAKE UP Control Registers
  375. List of Message Buffers (ID Registers)
  376. List of Message Buffers (DLC Registers and Data Registers)
  377. Table 23-5 List of Message Buffers (Data Registers)
  378. Classifying CAN Controller Registers
  379. Control Status Register (CSR)
  380. Fig. 23.2 Node Status Transition Diagram
  381. Bus Operation Stop Bit (HALT = 1)
  382. Last Event Indicate Register (LEIR)
  383. Receive and Transmit Error Counters (RTEC)
  384. Bit Timing Register (BTR)
  385. Message Buffer Valid Register (BVALR)
  386. Transmission Request Register (TREQR)
  387. Remote Frame Receiving Wait Register (RFWTR)
  388. Transmission Complete Register (TCR)
  389. Reception Complete Register (RCR)
  390. Receive Overrun Register (ROVRR)
  391. Acceptance Mask Select Register (AMSR)
  392. Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
  393. Message Buffers
  394. ID Register x (x = 0 to 15) (IDRx)
  395. DLC Register x (x = 0 to 15) (DLCRx)
  396. Data Register x (x = 0 to 15) (DTRx)
  397. CAN WAKE UP Control Register (CWUCR)
  398. Transmission of CAN Controller
  399. Fig. 23.5 Transmission Flowchart of the CAN Controller
  400. Reception of CAN Controller
  401. Fig. 23.6 Flowchart Determining Message Buffer (x) where Receive Messages Stored
  402. Reception Flowchart for CAN Controller
  403. How to Use CAN Controller
  404. Procedure for Transmission by Message Buffer (x)
  405. Procedure for Reception by Message Buffer (x)
  406. Setting Configuration of Multi-level Message Buffer
  407. Fig. 23.9 Examples of Operation of Multi-level Message Buffer
  408. CAN WAKE UP Function
  409. Chapter 24 Low Voltage and CPU Operation Detection Reset Circuit
  410. Overview of Low Voltage and CPU Operation Detection Reset Circuit
  411. Configuration of Low Voltage and CPU Operation Detection Reset Circuit
  412. Register for Low Voltage and CPU Operation Detection Reset Circuit
  413. Operation of Low Voltage and CPU Operation Detection Reset Circuit
  414. Cautions when Using Low Voltage and CPU Operation Detection Reset Circuit
  415. Sample Program for Low Voltage and CPU Operation Detection Reset Circuit
  416. Chapter 25 1-Mbit Flash Memory
  417. Overview of 1-Mbit Flash Memory
  418. Block Diagram for Entire Flash Memory and Flash Memory Sector Configuration
  419. Fig. 25.2 Sector Configuration of 1-Mbit Flash Memory
  420. Program/Erase Mode
  421. Table 25-1 Flash Memorr Control Signals
  422. Flash Memory Control Status Register (FMCS)
  423. Start Automatic Algorithm of Flash Memory
  424. Table 25-3 Bit Allocation of Hardware Sequence Flags
  425. Data Polling Flag (DQ7)
  426. Toggle Bit Flag (DQ6)
  427. Timing Limit Exceeding Flag (DQ5)
  428. Sector Erase Timer Flag (DQ3)
  429. Details of Programming to and Erasing from Flash Memory
  430. Data Programming to Flash Memory
  431. Fig. 25.3 Example of Data Programming Procedure
  432. All Data Erasing from Flash Memory (Chip Erase)
  433. Fig. 25.4 Example of Sector Erasing Procedure
  434. Sector Erasing Suspention
  435. Cautions when Using Flash Memory
  436. Sample Program for 1-Mbit Flash Memory
  437. Chapter 26 Examples of MB90F428/A Serial Write Connection
  438. Example of Serial Write Connection (User Power Supply Used)
  439. Example of Serial Write Connection (Power Supplied from the Writer)
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