OneStart

Menu

Hitachi H8S/2646R F-ZTAT manuals

H8S/2646R F-ZTAT first page preview

H8S/2646R F-ZTAT

Brand: Hitachi | Category: Desktop
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. section 1 overview
  18. Internal Block Diagram
  19. pin description
  20. Pin Functions in Each Operating Mode
  21. Pin Functions
  22. section 2 cpu
  23. Differences between H8S/2600 CPU and H8S/2000 CPU
  24. Differences from H8/300 CPU
  25. CPU Operating Modes
  26. Address Space
  27. Register Configuration
  28. General Registers
  29. Control Registers
  30. Initial Register Values
  31. data formats
  32. Memory Data Formats
  33. instruction set
  34. Instructions and Addressing Modes
  35. Table of Instructions Classified by Function
  36. Basic Instruction Formats
  37. Addressing Modes and Effective Address Calculation
  38. Effective Address Calculation
  39. Processing States
  40. Reset State
  41. Exception-Handling State
  42. Program Execution State
  43. basic timing
  44. On-Chip Supporting Module Access Timing
  45. On-Chip HCAN Module Access Timing
  46. External Address Space Access Timing
  47. Section 3 MCU Operating Modes
  49. System Control Register (SYSCR)
  50. Pin Function Control Register (PFCR)
  51. Operating Mode Descriptions
  53. section 4 exception handling
  54. Exception Handling Operation
  55. Reset
  56. Interrupts after Reset
  57. State of On-Chip Supporting Modules after Reset Release
  58. Interrupts
  59. Trap Instruction
  60. Stack Status after Exception Handling
  61. Notes on Use of the Stack
  62. Section 5 Interrupt Controller
  63. Block Diagram
  64. Pin Configuration
  65. Register Descriptions
  66. IRQ Enable Register (IER)
  67. IRQ Sense Control Registers H and L (ISCRH, ISCRL)
  68. IRQ Status Register (ISR)
  69. interrupt sources
  70. Internal Interrupts
  71. Interrupt Operation
  72. Interrupt Control Mode 0
  73. Interrupt Control Mode 2
  74. Interrupt Exception Handling Sequence
  75. Interrupt Response Times
  76. Usage Notes
  77. Instructions that Disable Interrupts
  78. Interrupts during Execution of EEPMOV Instruction
  79. Operation
  80. Section 6 PC Break Controller (PBC)
  83. Break Address Register B (BARB)
  84. Break Control Register B (BCRB)
  86. Notes on PC Break Interrupt Handling
  87. PC Break Operation in Continuous Data Transfer
  88. When Instruction Execution is Delayed by One State
  89. Additional Notes
  90. Section 7 Bus Controller
  94. Wait Control Registers H and L (WCRH, WCRL)
  95. Bus Control Register H (BCRH)
  96. Bus Control Register L (BCRL)
  98. Overview of Bus Control
  99. Bus Specifications
  100. Memory Interfaces
  101. Interface Specifications for Each Area
  102. Basic Bus Interface
  103. Valid Strobes
  105. Wait Control
  106. burst rom interface
  108. Idle Cycle
  109. Pin States During Idle Cycles
  110. Write Data Buffer Function
  111. bus arbitration
  112. Resets and the Bus Controller
  113. Section 8 Data Transfer Controller (DTC)
  117. DTC Mode Register B (MRB)
  118. DTC Source Address Register (SAR)
  119. DTC Transfer Count Register B (CRB)
  120. DTC Vector Register (DTVECR)
  121. Module Stop Control Register A (MSTPCRA)
  123. Activation Sources
  124. DTC Vector Table
  125. Location of Register Information in Address Space
  126. Normal Mode
  127. Repeat Mode
  128. Block Transfer Mode
  129. Chain Transfer
  130. Operation Timing
  131. Number of DTC Execution States
  132. Procedures for Using DTC
  133. Examples of Use of the DTC
  135. Section 9 I/O Ports
  136. Port
  150. Overview
  153. MOS Input Pull-Up Function
  178. Section 10 16-Bit Timer Pulse Unit (TPU)
  183. Timer Mode Register (TMDR)
  184. Timer I/O Control Register (TIOR)
  185. Timer Interrupt Enable Register (TIER)
  186. Timer Status Register (TSR)
  187. Timer Counter (TCNT)
  188. Timer General Register (TGR)
  189. Timer Start Register (TSTR)
  190. Timer Synchro Register (TSYR)
  192. Interface to Bus Master
  194. Basic Functions
  195. Synchronous Operation
  196. Buffer Operation
  197. Cascaded Operation
  198. PWM Modes
  199. Phase Counting Mode
  201. DTC Activation
  203. Interrupt Signal Timing
  205. Section 11 Programmable Pulse Generator (PPG)
  208. Registers
  210. Output Data Registers H and L (PODRH, PODRL)
  211. Next Data Registers H and L (NDRH, NDRL)
  212. PPG Output Control Register (PCR)
  213. PPG Output Mode Register (PMR)
  214. Port 1 Data Direction Register (P1DDR)
  216. Output Timing
  217. Normal Pulse Output
  218. Non-Overlapping Pulse Output
  219. Inverted Pulse Output
  220. Pulse Output Triggered by Input Capture
  222. Section 12 Watchdog Timer
  226. Reset Control/Status Register (RSTCSR)
  227. Notes on Register Access
  229. Interval Timer Operation
  230. Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
  232. Changing Value of PSS and CKS2 to CKS0
  233. Section 13 Serial Communication Interface (SCI)
  238. Transmit Shift Register (TSR)
  239. Serial Mode Register (SMR)
  240. Serial Control Register (SCR)
  241. Serial Status Register (SSR)
  242. Bit Rate Register (BRR)
  243. Smart Card Mode Register (SCMR)
  244. Module Stop Control Register B (MSTPCRB)
  246. Operation in Asynchronous Mode
  247. Multiprocessor Communication Function
  248. Operation in Clocked Synchronous Mode
  249. sci interrupts
  251. Section 14 Smart Card Interface
  260. Data Format
  261. Register Settings
  262. Clock
  263. Data Transfer Operations
  264. Operation in GSM Mode
  265. Operation in Block Transfer Mode
  267. Section 15 Hitachi Controller Area Network (HCAN)
  271. General Status Register (GSR)
  272. Bit Configuration Register (BCR)
  273. Mailbox Configuration Register (MBCR)
  274. Transmit Wait Register (TXPR)
  275. Transmit Wait Cancel Register (TXCR)
  276. Transmit Acknowledge Register (TXACK)
  277. Abort Acknowledge Register (ABACK)
  278. Receive Complete Register (RXPR)
  279. Remote Request Register (RFPR)
  280. Interrupt Register (IRR)
  281. Mailbox Interrupt Mask Register (MBIMR)
  282. Interrupt Mask Register (IMR)
  283. Receive Error Counter (REC)
  284. Unread Message Status Register (UMSR)
  285. Local Acceptance Filter Masks (LAFML, LAFMH)
  286. Message Control (MC0 to MC15)
  287. Message Data (MD0 to MD15)
  289. Transmit Mode
  290. Receive Mode
  291. HCAN Sleep Mode
  292. HCAN Halt Mode
  293. Interrupt Interface
  294. DTC Interface
  295. CAN Bus Interface
  296. Section 16 A/D Converter
  301. A/D Control/Status Register (ADCSR)
  302. A/D Control Register (ADCR)
  306. Scan Mode (SCAN = 1)
  307. Input Sampling and A/D Conversion Time
  308. External Trigger Input Timing
  310. Section 17 Motor Control PWM Timer
  315. PWM Output Control Registers 1 and 2 (PWOCR1, PWOCR2)
  316. PWM Polarity Registers 1 and 2 (PWPR1, PWPR2)
  317. PWM Counters 1 and 2 (PWCNT1, PWCNT2)
  318. PWM Duty Registers 1A, 1C, 1E, 1G (PWDTR1A, 1C, 1E, 1G)
  319. PWM Buffer Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G)
  320. PWM Buffer Registers 2A to 2D (PWBFR2A to PWBFR2D)
  321. Module Stop Control Register D (MSTPCRD)
  322. bus master interface
  324. PWM Channel 2 Operation
  325. Usage Note
  326. Section 18 LCD Controller/Driver
  330. LCD Control Register (LCR)
  331. LCD Control Register 2 (LCR2)
  334. Relationship between LCD RAM and Display
  335. Operation in Power-Down Modes
  336. Boosting the LCD Drive Power Supply
  337. Section 19 RAM
  340. Section 20 ROM
  342. Mode Transitions
  343. boot mode
  344. Flash Memory Emulation in RAM
  345. Differences between Boot Mode and User Program Mode
  346. Block Configuration
  347. pin configuration
  349. Flash Memory Control Register 2 (FLMCR2)
  350. Erase Block Register 1 (EBR1)
  351. RAM Emulation Register (RAMER)
  352. Flash Memory Power Control Register (FLPWCR)
  354. User Program Mode
  355. Flash Memory Programming/Erasing
  356. Program Mode
  357. Program-Verify Mode
  358. Erase Mode
  359. Protection
  360. Software Protection
  361. Error Protection
  363. Interrupt Handling when Programming/Erasing Flash Memory
  364. Socket Adapter Pin Correspondence Diagram
  365. Programmer Mode Operation
  366. Memory Read Mode
  367. Auto-Program Mode
  368. Auto-Erase Mode
  369. Status Read Mode
  370. Status Polling
  371. Notes on Memory Programming
  372. Flash Memory and Power-Down States
  373. Flash Memory Programming and Erasing Precautions
  374. Section 21 Clock Pulse Generator
  376. Low-Power Control Register (LPWRCR)
  377. Oscillator
  378. PLL Circuit
  379. Subclock Oscillator
  380. Subclock Waveform Generation Circuit
  381. Section 22 Power-Down Modes
  384. System Clock Control Register (SCKCR)
  386. Timer Control/Status Register (TCSR)
  387. Module Stop Control Register (MSTPCR)
  388. Medium-Speed Mode
  389. sleep mode
  390. Module Stop Mode
  392. Software Standby Mode
  393. Setting Oscillation Stabilization Time after Clearing Software Standby Mode
  395. Hardware Standby Mode
  396. Hardware Standby Mode Timing
  397. Exiting Watch Mode
  398. Sub-Sleep Mode
  399. Sub-Active Mode
  400. Direct Transitions
  402. section 23 electrical characteristics
  403. Power Supply Voltage and Operating Frequency Range
  404. DC Characteristics
  405. AC Characteristics
  406. Clock Timing
  407. Control Signal Timing
  408. Bus Timing
  409. Timing of On-Chip Supporting Modules
  410. A/D Conversion Characteristics
  411. LCD Characteristics
  412. Flash Memory Characteristics
  413. Appendix A Instruction Set
  414. A.2 Instruction Codes
  415. A.3 Operation Code Map
  416. A.4 Number of States Required for Instruction Execution
  417. A.5 Bus States During Instruction Execution
  418. A.6 Condition Code Modification
  419. Appendix B Internal I/O Register
  420. B.2 Functions
  421. Appendix C I/O Port Block Diagrams
  422. C.2 Port 2 Block Diagrams
  423. C.3 Port 3 Block Diagrams
  424. C.4 Port 4 Block Diagram
  425. C.5 Port 5 Block Diagrams
  426. C.6 Port 9 Block Diagram
  427. C.7 Port A Block Diagram
  428. C.8 Port B Block Diagram
  429. C.9 Port C Block Diagram
  430. C.10 Port D Block Diagram
  431. C.11 Port E Block Diagram
  432. C.12 Port F Block Diagrams
  433. C.13 Port G Block Diagram
  434. C.14 Port J Block Diagram
  435. C.15 Port K Block Diagram
  436. Appendix D Pin States
  437. Appendix F Package Dimensions
Related products
H8S/2648R F-ZTATH8S/2646H8S/2647H8S/2648H8S/2645HF-W6500HF-W2000HF-W7500HF-BX1000HF-BX1200
Hitachi categories
Air Conditioner
Inverter
Refrigerator
Storage
Projector
TV
Heat Pump
LCD TV
Camcorder
Trimmer
More Hitachi categories
Product
Menu
Learn More
Menu
Legal
Menu
Copyright © 2024 OneStart. All Rights Reserved