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Fujitsu F2MC-8L F202RA manuals

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F2MC-8L F202RA

Brand: Fujitsu | Category: Computer Hardware
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. CHAPTER 1 OVERVIEW
  8. Features of MB89202/F202RA Series
  9. MB89202/F202RA Series Product Lineup
  10. Differences between Models
  11. Block Diagram of MB89202/F202RA Series
  12. Pin Assignment
  13. Package Dimensions
  14. chapter 1 overview
  15. Pin Functions Description
  16. I/O Circuit Types
  17. CHAPTER 2 HANDLING DEVICES
  18. Precautions on Handling Devices
  19. CHAPTER 3 CPU
  20. Memory Space
  21. memory map
  22. Specific-purpose Areas
  23. Location of 16-bit Data on Memory
  24. Dedicated Register
  25. Condition Code Register (CCR)
  26. Register Bank Pointer (RP)
  27. General-Purpose Registers
  28. features of the general-purpose registers
  29. Interrupts
  30. Interrupt Level Setting Registers (ILR1 to ILR4)
  31. Steps in the Interrupt Operation
  32. Multiple Interrupts
  33. Interrupt Processing Time
  34. Stack Operation at Interrupt Processing
  35. Stack Area for Interrupt Processing
  36. Reset
  37. Reset Flag Register (RSFR)
  38. External Reset Pin
  39. Reset Operation
  40. mode fetch
  41. State of Each Pin at Reset
  42. Clock
  43. Clock Generator
  44. Clock Controller
  45. System Clock Control Register (SYCC)
  46. Clock Mode
  47. operations in active mode
  48. Oscillation Stabilization Wait Time
  49. Standby Mode (Low-Power Consumption Mode)
  50. Operations in Standby Mode
  51. Sleep Mode
  52. Stop Mode
  53. Standby Control Register (STBC)
  54. Diagram for State Transition in Standby Mode
  55. Notes on Standby Mode
  56. Memory Access Mode
  57. CHAPTER 4 I/O PORTS
  58. Overview of I/O Ports
  59. PORT
  60. Registers of Port 0 (PDR0, DDR0, and PUL0)
  61. Operations of Port 0 Functions
  62. Registers of Port 3 (PDR3, DDR3, PUL3)
  63. Operations of Port 3 Functions
  64. block diagram of port 4
  65. Registers of Port 4 (PDR4)
  66. Operations of Port 4 Functions
  67. block diagram of port 5
  68. Registers of Port 5 (PDR5, DDR5, PUL5)
  69. Operations of Port 5 Functions
  70. Registers of Port 6 (PDR6, DDR6, PUL6)
  71. Operations of Port 6 Functions
  72. block diagram of port 7
  73. Registers of Port 7 (PDR7, DDR7, PUL7)
  74. Operations of Port 7 Functions
  75. Programming Example of I/O Port
  76. CHAPTER 5 TIME-BASE TIMER
  77. Overview of Time-base Timer
  78. Configuration of Time-base Timer
  79. Time-base Timer Control Register (TBTC)
  80. Interrupt of Time-base Timer
  81. Operations of Time-base Timer Functions
  82. Notes on Using Time-base Timer
  83. Program Example for Time-base Timer
  84. CHAPTER 6 WATCHDOG TIMER
  85. Overview of Watchdog Timer
  86. Configuration of Watchdog Timer
  87. Watchdog Control Register (WDTC)
  88. Operations of Watchdog Timer Functions
  89. Notes on Using Watchdog Timer
  90. Program Example for Watchdog Timer
  91. CHAPTER 7 8-BIT PWM TIMER
  92. Overview of 8-bit PWM Timer
  93. pwm timer functions
  94. Configuration of 8-bit PWM Timer
  95. Pin of 8-bit PWM Timer
  96. Registers of 8-bit PWM Timer
  97. PWM Control Register (CNTR)
  98. PWM Compare Register (COMR)
  99. Interrupt of 8-bit PWM Timer
  100. Operations of the Interval Timer Functions
  101. Operations of the 8-bit PWM Timer Functions
  102. States in Each Mode During Operation
  103. Notes on Using 8-bit PWM Timer
  104. Program Example for PWM Timer
  105. program example of pwm timer functions
  106. CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
  107. Overview of 8/16-bit Capture Timer/Counter
  108. Configuration of 8/16-bit Capture Timer/Counter
  109. Pins of 8/16-bit Capture Timer/Counter
  110. Registers of 8/16-bit Capture Timer/Counter
  111. Capture Control Register (TCCR)
  112. Timer 0 Control Register (TCR0)
  113. Timer 1 Control Register (TCR1)
  114. Timer Output Control Register (TCR2)
  115. Timer 0 Data Register (TDR0)
  116. Timer 1 Data Register (TDR1)
  117. Capture Data Registers H and L (TCPH and TCPL)
  118. bit Capture Timer/Counter of Interrupts
  119. Explanation of Operations of Interval Timer Functions
  120. Operation of Counter Functions
  121. Functions of Operations of Capture Functions
  122. bit Capture Timer/Counter Operation in Each Mode
  123. Notes on Using 8/16-bit Capture Timer/Counter
  124. Program Example for 8/16-bit Capture Timer/Counter
  125. program example of counter function
  126. CHAPTER 9 12-BIT PPG TIMER
  127. Overview of 12-bit PPG Timer
  128. Configuration of 12-bit PPG Timer Circuit
  129. Pin of 12-bit PPG Timer
  130. Registers of 12-bit PPG Timer
  131. bit PPG Control Register 1 (RCR21)
  132. bit PPG Control Register 2 (RCR22)
  133. bit PPG Control Register 3 (RCR23)
  134. bit PPG Control Register 4 (RCR24)
  135. Operations of 12-bit PPG Timer Functions
  136. Notes on Using 12-bit PPG Timer
  137. Program Example for 12-bit PPG Timer
  138. CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
  139. Overview of External Interrupt Circuit 1
  140. Configuration of External Interrupt Circuit 1
  141. Pins of External Interrupt Circuit 1
  142. Registers of External Interrupt Circuit 1
  143. External Interrupt Control Register 1 (EIC1)
  144. External Interrupt Control Register 2 (EIC2)
  145. Interrupt of External Interrupt Circuit 1
  146. Operations of External Interrupt Circuit 1
  147. Program Example for External Interrupt Circuit 1
  148. CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
  149. Overview of External Interrupt Circuit 2
  150. Configuration of External Interrupt Circuit 2
  151. Pins of External Interrupt Circuit 2
  152. Registers of External Interrupt Circuit 2
  153. External Interrupt 2 Control Register (EIE2)
  154. External Interrupt 2 Flag Register (EIF2)
  155. Interrupt of External Interrupt Circuit 2
  156. Operations of External Interrupt Circuit 2
  157. Program Example for External Interrupt Circuit 2
  158. CHAPTER 12 A/D CONVERTER
  159. Overview of A/D Converter
  160. Configuration of A/D Converter
  161. Pins of A/D Converter
  162. Registers of A/D Converter
  163. A/D Control Register 1 (ADC1)
  164. A/D Control Register 2 (ADC2)
  165. A/D Data Register (ADDH and ADDL)
  166. A/D Enable Register (ADEN)
  167. Interrupt of A/D Converter
  168. Operations of A/D Converter Functions
  169. operations of a/d conversion functions
  170. Notes on Using A/D Converter
  171. Program Example for A/D Converter
  172. CHAPTER 13 UART
  173. Overview of UART
  174. Configuration of UART
  175. Pins of UART
  176. Registers of UART
  177. Serial Mode Control Register (SMC)
  178. Serial Rate Control Register (SRC)
  179. Serial Status and Data Register (SSD)
  180. receiving status
  181. Serial Input Data Register (SIDR)
  182. Serial Output Data Register (SODR)
  183. Clock Divider Selection Register (UPC)
  184. Serial Switch Register (SSEL)
  185. Interrupt of UART
  186. Operations of UART Functions
  187. Transmission Operations (Operating Mode 0, 1, 2, and 3)
  188. Reception Operations (Operating Mode 0, 1, or 3)
  189. Reception Operations (Operating Mode 2 Only)
  190. Program Example for UART
  191. CHAPTER 14 8-BIT SERIAL I/O
  192. Overview of 8-Bit Serial I/O
  193. Configuration of 8-Bit Serial I/O
  194. Pins of 8-Bit Serial I/O
  195. Registers of 8-Bit Serial I/O
  196. Serial Mode Register (SMR)
  197. Serial Data Register (SDR)
  198. Interrupt of 8-Bit Serial I/O
  199. Operations of Serial Output Functions
  200. operation at serial output completion
  201. Operations of Serial Input Functions
  202. operation at serial input completion
  203. Bit Serial I/O Operation in Each Mode
  204. when the external shift clock is used
  205. Notes on Using 8-Bit Serial I/O
  206. Example of 8-Bit Serial I/O Connection
  207. Program Example for 8-Bit Serial I/O
  208. program example for 8-bit serial input
  209. CHAPTER 15 BUZZER OUTPUT
  210. Overview of the Buzzer Output
  211. Configuration of the Buzzer Output
  212. Pin of the Buzzer Output
  213. Buzzer Register (BZCR)
  214. Program Example for Buzzer Output
  215. CHAPTER 16 WILD REGISTER FUNCTION
  216. Overview of the Wild Register Function
  217. Configuration of the Wild Register Function
  218. Registers of the Wild Register Function
  219. Data Setting Registers (WRDR0 and WRDR1)
  220. Higher Address Set Registers (WRARH0 and WRARH1)
  221. Lower Address Set Registers (WRARL0 and WRARL1)
  222. Address Comparison EN Register (WREN)
  223. Data Test Set Register (WROR)
  224. Operations of the Wild Register Functions
  225. CHAPTER 17 FLASH MEMORY
  226. Overview of Flash Memory
  227. Flash Memory Control Status Register (FMCS)
  228. Starting the Flash Memory Automatic Algorithm
  229. Confirming the Automatic Algorithm Execution State
  230. Data Polling Flag (DQ7)
  231. Toggle Bit Flag (DQ6)
  232. Timing Limit Exceeded Flag (DQ5)
  233. Toggle Bit-2 Flag (DQ2)
  234. Detailed Explanation of Writing to Erasing Flash Memory
  235. Setting The Read/Reset State
  236. Writing Data
  237. Erasing All Data (Erasing Chips)
  238. Flash Security Feature
  239. Notes on using Flash Memory
  240. APPENDIX
  241. APPENDIX A I/O Map
  242. APPENDIX B Overview of the Instructions
  243. B.1 Addressing
  244. B.2 Special Instructions
  245. B.3 Bit Manipulation Instructions (SETB and CLRB)
  246. transfer instructions
  247. operation instructions
  248. branch instructions
  249. other instructions
  250. B.5 Instruction Map
  251. APPENDIX C Mask Options
  252. APPENDIX D Programming EPROM with Evaluation Chip
  253. APPENDIX E Pin State of the MB89202/F202RA Series
  254. INDEX
  255. Table Of Contents
  256. Table Of Contents
  257. Table Of Contents
  258. Table Of Contents
  259. Table Of Contents
  260. Table Of Contents
  261. Table Of Contents
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