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Xilinx LogiCORE IP CAN 3.2 Getting Started Manual

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Contents
  1. revision history
  2. Table Of Contents
  3. Table Of Contents
  4. Schedule of Figures
  5. Guide Contents
  6. Online Document
  7. About the Core
  8. Recommended Design Experience
  9. Before you Begin
  10. Full
  11. Overview
  12. Generating the Core
  13. Implementing the Example Design
  14. Functional Simulation
  15. Directory and File Contents
  16. component_name>example design
  17. component_name>/implement
  18. component_name>/simulation/functional
  19. simulation/timing
  20. Implementation Scripts
  21. Timing Simulation
  22. Demonstration Test Bench
  23. Customizing the Demonstration Test Bench
Xilinx LogiCORE IP CAN 3.2 Getting Started Manual Manual pdf 17 page image
CAN Getting Started Guide www.xilinx.com 17UG186 April 19, 2010Chapter 4Detailed Example DesignThis chapter provides detailed information about the example design, including adescription of files and the directory structure generated by the Xilinx CORE Generator™software, the purpose and contents of the provided scripts, the contents of the exampleHDL wrappers, and the operation of the demonstration test bench.top directory link - white text invisibletopdirectoryTop-level project directory; name is user-defined/Core release notes file/docProduct documentationexample designVerilog and VHDL design files/implementImplementation script files/implement/resultsResults directory, created after implementation scripts are run, andcontains implement script results/simulationSimulation scripts/simulation/functionalFunctional simulation filessimulation/timingSimulation files
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